ALERT_HANDLER Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.114m	4.305ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.280s	537.888us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.400s	348.442us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.818m	22.793ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.878m	4.139ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	17.140s	1.075ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.400s	348.442us	20	20	100.00
		alert_handler_csr_aliasing	4.878m	4.139ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.766m	14.809ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.230m	1.214ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.340m	109.079ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.025m	967.910us	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.114m	4.305ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.267m	5.006ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.090m	905.391us	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.413m	13.243ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.153m	123.928ms	49	50	98.00
		alert_handler_lpg_stub_clk	59.390m	568.255ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.143h	321.339ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.282m	2.161ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.600s	185.631us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.040s	23.221us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	23.900s	752.988us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	23.900s	752.988us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.280s	537.888us	5	5	100.00
		alert_handler_csr_rw	9.400s	348.442us	20	20	100.00
		alert_handler_csr_aliasing	4.878m	4.139ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.020s	982.258us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.280s	537.888us	5	5	100.00
		alert_handler_csr_rw	9.400s	348.442us	20	20	100.00
		alert_handler_csr_aliasing	4.878m	4.139ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.020s	982.258us	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.936m	8.835ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.936m	8.835ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.936m	8.835ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.936m	8.835ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.699m	17.299ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
		alert_handler_tl_intg_err	1.441m	1.294ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.441m	1.294ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.936m	8.835ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.114m	4.305ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.114m	4.305ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.114m	4.305ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.114m	4.305ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.025m	967.910us	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.153m	123.928ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.025m	967.910us	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.340m	109.079ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.340m	109.079ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	51.320s	1.207ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.570m	6.465ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			824	850	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	11	73.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.71	97.09	100.00	100.00	99.38	99.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test alert_handler_stress_all_with_rand_reset has 21 failures.
  - 1.alert_handler_stress_all_with_rand_reset.22442562459732589192871735214735955240657704096698421287821363460139457634773
    Line 1742, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1123386850 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1123386850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.alert_handler_stress_all_with_rand_reset.40870645922460567559223213754432380505662717025118057926280158662008338241517
    Line 490, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 218338054 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 218338054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test alert_handler_lpg has 1 failures.
  - 24.alert_handler_lpg.80800794528904260413549657178563930860834151932553828107564766633375653770367
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_lpg/latest/run.log
```
  Job ID: smart:9c74ec0a-1de3-47ce-82d9-cf942ced3f3a
```
- Test alert_handler_entropy has 1 failures.
  - 34.alert_handler_entropy.4998815066751138622333575321656817635252749420705116577277825205595784457141
    Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_entropy/latest/run.log
```
  Job ID: smart:365e33b9-a51a-44e7-90c6-a721003a925e
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 3.alert_handler_sig_int_fail.1702883024965523947545700271047309143027636769616509205814810211723166973875
    Line 335, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  60057940 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @  60057940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 5.alert_handler_stress_all_with_rand_reset.58001328043813395032968334149755715722754659030595836298712038034644292866925
    Line 8189, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5286186501 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5286186501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:501) [alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 20.alert_handler_stress_all.9881092137523678755801589364836693403307366045301802309631738707498579497754
    Line 82385, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 57010778031 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.alert_handler_sig_int_fail_vseq] Check failed data & ~ro_mask == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 57010778031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `098010d125`