ALERT_HANDLER Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.148m	4.872ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.610s	229.717us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	10.300s	128.906us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.989m	23.730ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.142m	3.454ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	16.490s	1.388ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	10.300s	128.906us	20	20	100.00
		alert_handler_csr_aliasing	4.142m	3.454ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.904m	20.148ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.233m	1.191ms	50	50	100.00
V2	entropy	alert_handler_entropy	49.563m	48.308ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.187m	1.145ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.148m	4.872ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.029m	2.009ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.173m	1.139ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.576m	17.855ms	50	50	100.00
V2	lpg	alert_handler_lpg	51.726m	52.322ms	50	50	100.00
		alert_handler_lpg_stub_clk	51.898m	55.182ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	59.375m	259.349ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.198m	24.996ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.310s	50.081us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.260s	31.013us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.830s	1.042ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.830s	1.042ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.610s	229.717us	5	5	100.00
		alert_handler_csr_rw	10.300s	128.906us	20	20	100.00
		alert_handler_csr_aliasing	4.142m	3.454ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.740s	2.148ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.610s	229.717us	5	5	100.00
		alert_handler_csr_rw	10.300s	128.906us	20	20	100.00
		alert_handler_csr_aliasing	4.142m	3.454ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.740s	2.148ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.287m	29.319ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.287m	29.319ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.287m	29.319ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.287m	29.319ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.066m	65.842ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
		alert_handler_tl_intg_err	1.381m	9.865ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.381m	9.865ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.287m	29.319ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.148m	4.872ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.148m	4.872ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.148m	4.872ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.148m	4.872ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.187m	1.145ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	51.726m	52.322ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.187m	1.145ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	49.563m	48.308ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	49.563m	48.308ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.106m	1.867ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.291m	19.374ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			832	850	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.73	97.09	100.00	100.00	99.38	99.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
  • Test alert_handler_stress_all_with_rand_reset has 17 failures.

    • 0.alert_handler_stress_all_with_rand_reset.74458715503831917421652428536483547248161163483775974863624982948303334707218
      Line 994, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 597649558 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 597649558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.102383715788664461876373478434137975389953151076919450677000321054880593664610
      Line 4575, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3547032079 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3547032079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 31.alert_handler_stress_all_with_rand_reset.6471226377746214851542439862516799394879054540369914294159052566763910465206
      Line 3748, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3816444880 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3816444880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.14_08.53.29
• 2024.08.13_08.17.59
• 2024.08.12_08.47.00
• 2024.08.11_08.32.53
• 2024.08.10_08.40.03
• 2024.08.09_08.09.01