ALERT_HANDLER Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.204m	4.652ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.970s	254.971us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.720s	136.028us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.309m	40.809ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.967m	41.596ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	16.110s	876.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.720s	136.028us	20	20	100.00
		alert_handler_csr_aliasing	5.967m	41.596ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.521m	8.077ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.237m	2.239ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.520m	230.770ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.281m	4.458ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.204m	4.652ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.113m	1.110ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.117m	4.348ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.168m	66.061ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.180m	62.946ms	50	50	100.00
		alert_handler_lpg_stub_clk	45.860m	69.767ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.231h	329.478ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	38.920s	3.321ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.860s	59.403us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.750s	13.771us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	27.310s	1.281ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	27.310s	1.281ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.970s	254.971us	5	5	100.00
		alert_handler_csr_rw	9.720s	136.028us	20	20	100.00
		alert_handler_csr_aliasing	5.967m	41.596ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.410s	2.764ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.970s	254.971us	5	5	100.00
		alert_handler_csr_rw	9.720s	136.028us	20	20	100.00
		alert_handler_csr_aliasing	5.967m	41.596ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.410s	2.764ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.570m	4.921ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.570m	4.921ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.570m	4.921ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.570m	4.921ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.667m	32.505ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
		alert_handler_tl_intg_err	1.164m	1.092ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.164m	1.092ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.570m	4.921ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.204m	4.652ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.204m	4.652ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.204m	4.652ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.204m	4.652ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.281m	4.458ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.180m	62.946ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.281m	4.458ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.520m	230.770ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.520m	230.770ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.140s	886.450us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.348m	11.685ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			836	850	98.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.75	97.09	100.00	100.00	99.38	99.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:

  • Test alert_handler_stress_all_with_rand_reset has 12 failures.

    • 0.alert_handler_stress_all_with_rand_reset.36106223178373692468517797688199936413973554619169215340810431406675526150177
      Line 1078, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3306974496 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3306974496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.41819639082767062157184084407377387427995383969769642167794733102230662569862
      Line 501, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 795126966 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 795126966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 31.alert_handler_stress_all.21750816687955113541754650716241914489458524516209245052318972062142542289868
      Line 666, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 430255722 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (37 [0x25] vs 187 [0xbb])
        UVM_INFO @ 430255722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 40.alert_handler_stress_all_with_rand_reset.59553615952357221668122578559247664935334817621710886165683312271313927637339
      Line 8487, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16908947847 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 16908947847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.15_05.49.10
• 2024.08.14_08.53.29
• 2024.08.13_08.17.59
• 2024.08.12_08.47.00
• 2024.08.11_08.32.53
• 2024.08.10_08.40.03