ALERT_HANDLER Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.007m	983.865us	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.550s	118.987us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.290s	259.971us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.988m	23.818ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.966m	8.473ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.650s	1.054ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.290s	259.971us	20	20	100.00
		alert_handler_csr_aliasing	4.966m	8.473ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.772m	6.169ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.314m	5.016ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.509m	478.427ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.048m	991.436us	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.007m	983.865us	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.239m	5.203ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.196m	5.097ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.050m	177.260ms	50	50	100.00
V2	lpg	alert_handler_lpg	45.815m	94.473ms	49	50	98.00
		alert_handler_lpg_stub_clk	52.764m	55.211ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.131h	144.773ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.478m	8.258ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.510s	165.431us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.910s	21.827us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.420s	921.806us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.420s	921.806us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.550s	118.987us	5	5	100.00
		alert_handler_csr_rw	9.290s	259.971us	20	20	100.00
		alert_handler_csr_aliasing	4.966m	8.473ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.180s	3.069ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.550s	118.987us	5	5	100.00
		alert_handler_csr_rw	9.290s	259.971us	20	20	100.00
		alert_handler_csr_aliasing	4.966m	8.473ms	5	5	100.00
		alert_handler_same_csr_outstanding	47.180s	3.069ms	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.055m	6.086ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.055m	6.086ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.055m	6.086ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.055m	6.086ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.534m	32.636ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
		alert_handler_tl_intg_err	1.124m	2.167ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.124m	2.167ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.055m	6.086ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.007m	983.865us	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.007m	983.865us	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.007m	983.865us	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.007m	983.865us	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.048m	991.436us	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	45.815m	94.473ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.048m	991.436us	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.509m	478.427ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.509m	478.427ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.299m	2.311ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	10.219m	20.347ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			829	850	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.65	97.09	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 2.alert_handler_stress_all_with_rand_reset.72551332317848312420430380652314511509663149174031916942593115025590319819110
      Line 2079, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1517683000 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1517683000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.alert_handler_stress_all_with_rand_reset.29861619673751930478058055728209400518049915459296287701023767942238497037953
      Line 4164, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25327914108 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 25327914108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 9.alert_handler_stress_all_with_rand_reset.87855838671653057943192214069266056765672314212310764179818336033755679503692
      Line 3024, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3153235520 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3153235520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.alert_handler_stress_all_with_rand_reset.107742561152824014628231967934810430589882720407353291754226152543314006634186
      Line 3571, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6272116741 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 6272116741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 19.alert_handler_lpg.5004141360525133543992532953100839278769731769902479919674094390256948595801
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_lpg/latest/run.log

        Job ID: smart:154cc994-85cc-4f82-ae0f-98e13a10d038
      

Past Results

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• 2024.08.16_08.50.24
• 2024.08.15_05.49.10
• 2024.08.14_08.53.29
• 2024.08.13_08.17.59
• 2024.08.12_08.47.00
• 2024.08.11_08.32.53