ALERT_HANDLER Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.190m 4.584ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 9.680s 104.481us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 8.950s 515.536us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 8.388m 8.822ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 4.104m 4.061ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 14.580s 663.108us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 8.950s 515.536us 20 20 100.00
alert_handler_csr_aliasing 4.104m 4.061ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 4.714m 29.768ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.266m 3.258ms 50 50 100.00
V2 entropy alert_handler_entropy 58.023m 231.710ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 1.099m 3.169ms 50 50 100.00
V2 clk_skew alert_handler_smoke 1.190m 4.584ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.114m 821.229us 50 50 100.00
V2 random_classes alert_handler_random_classes 1.327m 5.402ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 14.082m 78.389ms 50 50 100.00
V2 lpg alert_handler_lpg 51.209m 221.199ms 50 50 100.00
alert_handler_lpg_stub_clk 59.282m 118.989ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.181h 136.293ms 50 50 100.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 1.124m 22.512ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.440s 50.460us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.740s 12.778us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 32.890s 739.708us 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 32.890s 739.708us 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 9.680s 104.481us 5 5 100.00
alert_handler_csr_rw 8.950s 515.536us 20 20 100.00
alert_handler_csr_aliasing 4.104m 4.061ms 5 5 100.00
alert_handler_same_csr_outstanding 50.600s 2.836ms 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 9.680s 104.481us 5 5 100.00
alert_handler_csr_rw 8.950s 515.536us 20 20 100.00
alert_handler_csr_aliasing 4.104m 4.061ms 5 5 100.00
alert_handler_same_csr_outstanding 50.600s 2.836ms 20 20 100.00
V2 TOTAL 630 630 100.00
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 5.412m 9.779ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 5.412m 9.779ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 5.412m 9.779ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 5.412m 9.779ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 17.548m 50.113ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
alert_handler_tl_intg_err 1.498m 11.205ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.498m 11.205ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 5.412m 9.779ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.190m 4.584ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.190m 4.584ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.190m 4.584ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.190m 4.584ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.099m 3.169ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 51.209m 221.199ms 50 50 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.099m 3.169ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 58.023m 231.710ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 58.023m 231.710ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 26.670s 2.436ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 9.958m 18.738ms 35 50 70.00
V3 TOTAL 35 50 70.00
TOTAL 835 850 98.24

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 15 100.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.23 99.99 98.67 97.09 100.00 100.00 99.38 99.48

Failure Buckets

Past Results