ALERT_HANDLER Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.131m	8.011ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.010s	584.704us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.210s	129.239us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.185m	17.116ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.810m	6.543ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.940s	581.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.210s	129.239us	20	20	100.00
		alert_handler_csr_aliasing	3.810m	6.543ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.311m	5.384ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.329m	5.142ms	50	50	100.00
V2	entropy	alert_handler_entropy	57.303m	61.392ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	58.370s	5.788ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.131m	8.011ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.272m	1.222ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.251m	1.258ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.368m	69.804ms	49	50	98.00
V2	lpg	alert_handler_lpg	54.239m	110.496ms	49	50	98.00
		alert_handler_lpg_stub_clk	52.205m	57.656ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.176h	279.189ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	52.980s	1.540ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.540s	57.678us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.980s	20.506us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	26.430s	435.950us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	26.430s	435.950us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.010s	584.704us	5	5	100.00
		alert_handler_csr_rw	9.210s	129.239us	20	20	100.00
		alert_handler_csr_aliasing	3.810m	6.543ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.140s	719.253us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.010s	584.704us	5	5	100.00
		alert_handler_csr_rw	9.210s	129.239us	20	20	100.00
		alert_handler_csr_aliasing	3.810m	6.543ms	5	5	100.00
		alert_handler_same_csr_outstanding	45.140s	719.253us	20	20	100.00
V2		TOTAL			626	630	99.37
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.385m	5.253ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.385m	5.253ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.385m	5.253ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.385m	5.253ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.750m	65.856ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
		alert_handler_tl_intg_err	1.238m	1.229ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.238m	1.229ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.385m	5.253ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.131m	8.011ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.131m	8.011ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.131m	8.011ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.131m	8.011ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	58.370s	5.788ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.239m	110.496ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	58.370s	5.788ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	57.303m	61.392ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	57.303m	61.392ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.028m	1.649ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	8.257m	4.132ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			830	850	97.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.99	98.80	97.09	100.00	100.00	99.38	99.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

  • Test alert_handler_stress_all_with_rand_reset has 13 failures.

    • 6.alert_handler_stress_all_with_rand_reset.112782829699881706174484211849575991798089341853845550200675101446866326264327
      Line 509, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 750325291 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 750325291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.alert_handler_stress_all_with_rand_reset.109445832302856157320871324930990307546209694312158011481820528468993951520110
      Line 1747, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1251788087 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10032 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1251788087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 2 failures:

  • Test alert_handler_stress_all has 2 failures.

    • 12.alert_handler_stress_all.101799088174882982703074138766015260716785250260210766379508132022645605889411
      Line 56899, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 18278682168 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 18278682168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.alert_handler_stress_all.27654385446360697687864803415914798346553580550475529158090578000445030924200
      Line 78908, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 50239862612 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 50239862612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 24.alert_handler_stress_all_with_rand_reset.4650858013785612141924159159781803877765310662615283167675369106640561738876
      Line 5319, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3364592032 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3364592032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.alert_handler_stress_all_with_rand_reset.83665764790042736099068062998499300620001599657179557817066073791666699151875
      Line 1409, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 935744581 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 935744581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:330) [scoreboard] Check failed cycle_cnt <= exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 22.alert_handler_ping_timeout.95614290125866795572673693672243287610143900847985283995013390188616710152925
      Line 507, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 7919600720 ps: (alert_handler_scoreboard.sv:330) [uvm_test_top.env.scoreboard] Check failed cycle_cnt <= exp_cycle (307 [0x133] vs 138 [0x8a])
        UVM_INFO @ 7919600720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_lpg has 1 failures.

    • 37.alert_handler_lpg.2129981365389830061731536633425319121353543663626874561051755893260875289067
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_lpg/latest/run.log

        Job ID: smart:48fb574a-371c-4e95-a14d-a7af21d28b2e
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 40.alert_handler_stress_all_with_rand_reset.66039579531250702619433667194344753768582669116882333103498444295421191620886
      Line 8890, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2299493361 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 3 [0x3]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 2299493361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.08.18_08.51.41
• 2024.08.17_07.33.37
• 2024.08.16_08.50.24
• 2024.08.15_05.49.10
• 2024.08.14_08.53.29
• 2024.08.13_08.17.59