ALERT_HANDLER Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 1.131m 8.011ms 50 50 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 10.010s 584.704us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 9.210s 129.239us 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 8.185m 17.116ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 3.810m 6.543ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 13.940s 581.331us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 9.210s 129.239us 20 20 100.00
alert_handler_csr_aliasing 3.810m 6.543ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 esc_accum alert_handler_esc_alert_accum 5.311m 5.384ms 50 50 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.329m 5.142ms 50 50 100.00
V2 entropy alert_handler_entropy 57.303m 61.392ms 50 50 100.00
V2 sig_int_fail alert_handler_sig_int_fail 58.370s 5.788ms 50 50 100.00
V2 clk_skew alert_handler_smoke 1.131m 8.011ms 50 50 100.00
V2 random_alerts alert_handler_random_alerts 1.272m 1.222ms 50 50 100.00
V2 random_classes alert_handler_random_classes 1.251m 1.258ms 50 50 100.00
V2 ping_timeout alert_handler_ping_timeout 11.368m 69.804ms 49 50 98.00
V2 lpg alert_handler_lpg 54.239m 110.496ms 49 50 98.00
alert_handler_lpg_stub_clk 52.205m 57.656ms 50 50 100.00
V2 stress_all alert_handler_stress_all 1.176h 279.189ms 48 50 96.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 52.980s 1.540ms 20 20 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 4.540s 57.678us 20 20 100.00
V2 intr_test alert_handler_intr_test 1.980s 20.506us 50 50 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 26.430s 435.950us 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 26.430s 435.950us 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 10.010s 584.704us 5 5 100.00
alert_handler_csr_rw 9.210s 129.239us 20 20 100.00
alert_handler_csr_aliasing 3.810m 6.543ms 5 5 100.00
alert_handler_same_csr_outstanding 45.140s 719.253us 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 10.010s 584.704us 5 5 100.00
alert_handler_csr_rw 9.210s 129.239us 20 20 100.00
alert_handler_csr_aliasing 3.810m 6.543ms 5 5 100.00
alert_handler_same_csr_outstanding 45.140s 719.253us 20 20 100.00
V2 TOTAL 626 630 99.37
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 5.385m 5.253ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 5.385m 5.253ms 20 20 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 5.385m 5.253ms 20 20 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 5.385m 5.253ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 19.750m 65.856ms 20 20 100.00
V2S tl_intg_err alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
alert_handler_tl_intg_err 1.238m 1.229ms 20 20 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.238m 1.229ms 20 20 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 5.385m 5.253ms 20 20 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 1.131m 8.011ms 50 50 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 1.131m 8.011ms 50 50 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 1.131m 8.011ms 50 50 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 1.131m 8.011ms 50 50 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 58.370s 5.788ms 50 50 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 54.239m 110.496ms 49 50 98.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 58.370s 5.788ms 50 50 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 57.303m 61.392ms 50 50 100.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 57.303m 61.392ms 50 50 100.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 1.028m 1.649ms 5 5 100.00
V2S TOTAL 65 65 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 8.257m 4.132ms 34 50 68.00
V3 TOTAL 34 50 68.00
TOTAL 830 850 97.65

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 12 80.00
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.26 99.99 98.80 97.09 100.00 100.00 99.38 99.56

Failure Buckets

Past Results