e45ccd274a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.153m | 1.320ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 8.510s | 196.180us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 9.710s | 497.113us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 6.916m | 16.091ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 4.623m | 17.926ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 12.430s | 237.249us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 9.710s | 497.113us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 4.623m | 17.926ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 6.044m | 11.131ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.332m | 4.976ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 56.367m | 233.103ms | 50 | 50 | 100.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.173m | 1.186ms | 48 | 50 | 96.00 |
| V2 | clk_skew | alert_handler_smoke | 1.153m | 1.320ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.279m | 1.300ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.395m | 5.000ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 9.712m | 57.049ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 51.938m | 222.841ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 50.113m | 167.498ms | 49 | 50 | 98.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.262h | 150.427ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.159m | 1.674ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.130s | 39.469us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.850s | 17.760us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 26.350s | 1.808ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 26.350s | 1.808ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 8.510s | 196.180us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.710s | 497.113us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.623m | 17.926ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 44.880s | 2.206ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 8.510s | 196.180us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 9.710s | 497.113us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 4.623m | 17.926ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 44.880s | 2.206ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 626 | 630 | 99.37 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 6.473m | 7.871ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 6.473m | 7.871ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 6.473m | 7.871ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 6.473m | 7.871ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 18.267m | 16.105ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.201m | 4.421ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.201m | 4.421ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 6.473m | 7.871ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.153m | 1.320ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.153m | 1.320ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.153m | 1.320ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.153m | 1.320ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.173m | 1.186ms | 48 | 50 | 96.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 51.938m | 222.841ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.173m | 1.186ms | 48 | 50 | 96.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 56.367m | 233.103ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 56.367m | 233.103ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 29.430s | 579.137us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 13.191m | 25.239ms | 37 | 50 | 74.00 |
| V3 | TOTAL | 37 | 50 | 74.00 | |||
| TOTAL | 833 | 850 | 98.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 12 | 80.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.25 | 99.99 | 98.72 | 97.09 | 100.00 | 100.00 | 99.38 | 99.60 |
UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
3.alert_handler_stress_all_with_rand_reset.115423221036381010057495881268073482552364129524305380047825519140323690784464
Line 3058, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1864992129 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1864992129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.alert_handler_stress_all_with_rand_reset.102398436198291084464435457742636169487596871433270474671700094847939285543189
Line 592, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 338874252 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 338874252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
21.alert_handler_stress_all_with_rand_reset.57627680284631062401329536415312846436801805855007786686038045098541340252988
Line 4950, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1650377814 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1650377814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.alert_handler_stress_all_with_rand_reset.31527349154085553132680014404696731247726445157399673978348608786928220841733
Line 3312, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9619662872 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9619662872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
11.alert_handler_sig_int_fail.2333316132551126874850322505157643456088242467739433459875073062993070437150
Line 338, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 42768293 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 42768293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
31.alert_handler_stress_all.29384369227877863172961673519071935328514751063620318818538390537656830624984
Line 73892, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 35941577137 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (695 [0x2b7] vs 671 [0x29f])
UVM_INFO @ 35941577137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_state has 1 failures:
41.alert_handler_sig_int_fail.43676101028558518110001033173935859549314276719928590622690563953880963760065
Line 417, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 58351205 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 6 [0x6]) reg name: alert_handler_reg_block.classb_state
UVM_INFO @ 58351205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
41.alert_handler_lpg_stub_clk.85936622752253824751007984213429679944482327576286600671652144133556667963694
Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest/run.log
Job ID: smart:3682c204-84e1-4d38-b171-a4c35b406f62