34b8fc33e3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.363m | 825.546us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 8.210s | 323.247us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 13.000s | 102.411us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.446m | 8.650ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 3.378m | 2.905ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 17.830s | 295.755us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 13.000s | 102.411us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 3.378m | 2.905ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 6.998m | 26.148ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.284m | 1.138ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 51.732m | 228.106ms | 49 | 50 | 98.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.612m | 2.240ms | 50 | 50 | 100.00 |
| V2 | clk_skew | alert_handler_smoke | 1.363m | 825.546us | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.548m | 1.188ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.669m | 7.416ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 12.710m | 144.286ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 58.130m | 56.874ms | 50 | 50 | 100.00 |
| alert_handler_lpg_stub_clk | 49.924m | 42.915ms | 50 | 50 | 100.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.173h | 70.646ms | 48 | 50 | 96.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.416m | 5.728ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 5.780s | 90.933us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 2.890s | 24.702us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 42.220s | 859.524us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 42.220s | 859.524us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 8.210s | 323.247us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 13.000s | 102.411us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 3.378m | 2.905ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 1.332m | 8.918ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 8.210s | 323.247us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 13.000s | 102.411us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 3.378m | 2.905ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 1.332m | 8.918ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 627 | 630 | 99.52 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 7.430m | 22.752ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 7.430m | 22.752ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 7.430m | 22.752ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 7.430m | 22.752ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 18.840m | 15.771ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.549m | 4.381ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.549m | 4.381ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 7.430m | 22.752ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.363m | 825.546us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.363m | 825.546us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.363m | 825.546us | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.363m | 825.546us | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.612m | 2.240ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 58.130m | 56.874ms | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.612m | 2.240ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 51.732m | 228.106ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 51.732m | 228.106ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 50.720s | 1.366ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 10.571m | 6.520ms | 31 | 50 | 62.00 |
| V3 | TOTAL | 31 | 50 | 62.00 | |||
| TOTAL | 828 | 850 | 97.41 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 13 | 86.67 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.24 | 99.99 | 98.66 | 97.06 | 100.00 | 100.00 | 99.38 | 99.56 |
UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
1.alert_handler_stress_all_with_rand_reset.44106170676798595100446627897073087405173662680617700422054293286329246388894
Line 2235, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7825069248 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7825069248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.alert_handler_stress_all_with_rand_reset.97813762910546946723769542243852255967866983084701579775906271675593106318587
Line 4853, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4396988339 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4396988339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
2.alert_handler_stress_all.58309124374027308370836826903960317090230903687268839814288729282913459623385
Line 8939, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/2.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 4713338132 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 4713338132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_state has 1 failures:
5.alert_handler_stress_all.16466761359574858675286184520228423035580686479132475371892224214368071688184
Line 57686, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/5.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 77980949852 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: alert_handler_reg_block.classa_state
UVM_INFO @ 77980949852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
15.alert_handler_entropy.104663994009396428006122417176396741414692752777985035690959506544655392601693
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/15.alert_handler_entropy/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
19.alert_handler_stress_all_with_rand_reset.100062558329736691126653102695325440391065984801622226642316003148993564391425
Line 10699, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37550750141 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 37550750141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---