ALERT_HANDLER Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	50.350s	1.461ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	7.360s	852.662us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	7.900s	467.702us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.344m	33.650ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.209m	3.696ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.240s	473.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	7.900s	467.702us	20	20	100.00
		alert_handler_csr_aliasing	3.209m	3.696ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.212m	29.209ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	55.940s	1.348ms	50	50	100.00
V2	entropy	alert_handler_entropy	39.976m	51.795ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	47.050s	4.427ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	50.350s	1.461ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	47.280s	7.125ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	49.060s	4.640ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	8.606m	68.607ms	50	50	100.00
V2	lpg	alert_handler_lpg	34.841m	286.678ms	50	50	100.00
		alert_handler_lpg_stub_clk	42.657m	230.559ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	51.066m	950.434ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.023m	8.699ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.000s	49.819us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.220s	43.927us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	20.470s	2.560ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	20.470s	2.560ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	7.360s	852.662us	5	5	100.00
		alert_handler_csr_rw	7.900s	467.702us	20	20	100.00
		alert_handler_csr_aliasing	3.209m	3.696ms	5	5	100.00
		alert_handler_same_csr_outstanding	38.350s	722.474us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	7.360s	852.662us	5	5	100.00
		alert_handler_csr_rw	7.900s	467.702us	20	20	100.00
		alert_handler_csr_aliasing	3.209m	3.696ms	5	5	100.00
		alert_handler_same_csr_outstanding	38.350s	722.474us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	4.791m	14.702ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	4.791m	14.702ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	4.791m	14.702ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	4.791m	14.702ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	14.656m	109.090ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
		alert_handler_tl_intg_err	1.069m	7.390ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.069m	7.390ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	4.791m	14.702ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	50.350s	1.461ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	50.350s	1.461ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	50.350s	1.461ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	50.350s	1.461ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	47.050s	4.427ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	34.841m	286.678ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	47.050s	4.427ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	39.976m	51.795ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	39.976m	51.795ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	18.890s	525.627us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	6.524m	9.492ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.23	99.99	98.63	97.06	100.00	100.00	99.38	99.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test alert_handler_stress_all_with_rand_reset has 18 failures.
  - 0.alert_handler_stress_all_with_rand_reset.97844794531584865276139669563274273479383281413580768756109942139348880445591
    Line 4378, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4022323958 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4022323958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.alert_handler_stress_all_with_rand_reset.1046355099051831213116006959547232189377745597134829624019274730759919413965
    Line 1813, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1050693074 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1050693074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 1.alert_handler_stress_all_with_rand_reset.65013748897853576612916113436067620908062481841866496856726347099921251699499
    Line 3524, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3362670826 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3362670826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.alert_handler_stress_all_with_rand_reset.40221090075145025847507037470982692871920006923258011411381241145956789640335
    Line 4199, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6046922949 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6046922949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_esc_cnt has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 15.alert_handler_sig_int_fail.74825772014168266743261352299144210184600156299711381561296009979208390167570
    Line 395, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @  62574286 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (70 [0x46] vs 290 [0x122]) reg name: alert_handler_reg_block.classb_esc_cnt
  UVM_INFO @  62574286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 28.alert_handler_stress_all.14519479507439353689780216278153514480904214984245151820326764662732873919065
    Line 74314, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/28.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 82601524522 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 82601524522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 49.alert_handler_stress_all.13320252905618600398022312371996756752265091491635947950457593182352767143291
    Line 65949, in log /workspaces/repo/scratch/os_regression_2024_08_22/alert_handler-sim-vcs/49.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 140550204079 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 140550204079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0825c81be0`