ALERT_HANDLER Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	2.021m	4.408ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	19.390s	129.441us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	15.180s	111.723us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.528m	4.275ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.320m	1.131ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	26.490s	196.668us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	15.180s	111.723us	20	20	100.00
		alert_handler_csr_aliasing	4.320m	1.131ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	9.504m	6.227ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.934m	2.465ms	50	50	100.00
V2	entropy	alert_handler_entropy	58.169m	38.941ms	38	50	76.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.776m	2.016ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	2.021m	4.408ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.682m	3.107ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.497m	6.015ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	15.676m	15.406ms	50	50	100.00
V2	lpg	alert_handler_lpg	52.991m	43.913ms	42	50	84.00
		alert_handler_lpg_stub_clk	58.930m	33.289ms	44	50	88.00
V2	stress_all	alert_handler_stress_all	1.399h	114.446ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.439m	1.513ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	7.040s	387.796us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.380s	27.548us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	41.760s	408.337us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	41.760s	408.337us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	19.390s	129.441us	5	5	100.00
		alert_handler_csr_rw	15.180s	111.723us	20	20	100.00
		alert_handler_csr_aliasing	4.320m	1.131ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.300m	1.440ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	19.390s	129.441us	5	5	100.00
		alert_handler_csr_rw	15.180s	111.723us	20	20	100.00
		alert_handler_csr_aliasing	4.320m	1.131ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.300m	1.440ms	20	20	100.00
V2		TOTAL			603	630	95.71
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	9.785m	68.572ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	9.785m	68.572ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	9.785m	68.572ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	9.785m	68.572ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	32.154m	63.863ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
		alert_handler_tl_intg_err	1.997m	4.991ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.997m	4.991ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	9.785m	68.572ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	2.021m	4.408ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	2.021m	4.408ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	2.021m	4.408ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	2.021m	4.408ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.776m	2.016ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.991m	43.913ms	42	50	84.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.776m	2.016ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.169m	38.941ms	38	50	76.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.169m	38.941ms	38	50	76.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.175m	1.095ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	16.540m	16.252ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			808	850	95.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	11	73.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.68	97.09	100.00	100.00	99.38	99.52

Failure Buckets

Job timed out after * minutes has 26 failures:
- Test alert_handler_lpg has 8 failures.
  - 0.alert_handler_lpg.51788061809008344780533998910674673825608609578828716963170209823576095590045
    Log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```
  - 11.alert_handler_lpg.70221763789739316279030763306817465989928143055381100140157776659922854391394
    Log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 6 more failures.
- Test alert_handler_lpg_stub_clk has 6 failures.
  - 0.alert_handler_lpg_stub_clk.15524340668539993037129671096779072871258771295749899607392719314731517016877
    Log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
  - 6.alert_handler_lpg_stub_clk.56496251015610953277065766551801323479483680502679589743833638990037890845899
    Log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 4 more failures.
- Test alert_handler_entropy has 12 failures.
  - 2.alert_handler_entropy.8834010325555279309676735773887740776901532309003410280237484473130334637487
    Log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_entropy/latest/run.log
```
  Job timed out after 60 minutes
```
  - 4.alert_handler_entropy.44421251868201054739645454515069523154542158863308329473510978181991829728274
    Log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_entropy/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 10 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test alert_handler_stress_all_with_rand_reset has 15 failures.
  - 0.alert_handler_stress_all_with_rand_reset.101177694161623360287158889619221394070277175368518155044509980537855922505825
    Line 5725, in log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 975926713 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 975926713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.alert_handler_stress_all_with_rand_reset.60225227633667552679031607105742366977288261741900219849613453434856177257377
    Line 2446, in log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6583954858 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6583954858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 0.alert_handler_sig_int_fail.10594719401879106406803981129906791436179046764430826144228387969051138765828
    Line 478, in log /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 229243416 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (200 [0xc8] vs 217 [0xd9])
  UVM_INFO @ 229243416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `e733a8ef8a`