ALERT_HANDLER Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.655m	4.679ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	14.090s	195.810us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	13.330s	184.054us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	3.981m	3.723ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	6.578m	76.557ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	22.310s	803.657us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	13.330s	184.054us	20	20	100.00
		alert_handler_csr_aliasing	6.578m	76.557ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.825m	10.083ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.266m	2.155ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.487m	256.000ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.262m	3.022ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.655m	4.679ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.584m	2.360ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.482m	5.167ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	16.419m	262.016ms	50	50	100.00
V2	lpg	alert_handler_lpg	53.193m	225.768ms	49	50	98.00
		alert_handler_lpg_stub_clk	53.074m	55.414ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.088h	285.223ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	54.430s	1.694ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	6.110s	75.909us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.850s	14.276us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	40.180s	381.468us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	40.180s	381.468us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	14.090s	195.810us	5	5	100.00
		alert_handler_csr_rw	13.330s	184.054us	20	20	100.00
		alert_handler_csr_aliasing	6.578m	76.557ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.247m	1.336ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	14.090s	195.810us	5	5	100.00
		alert_handler_csr_rw	13.330s	184.054us	20	20	100.00
		alert_handler_csr_aliasing	6.578m	76.557ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.247m	1.336ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	8.659m	39.486ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	8.659m	39.486ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	8.659m	39.486ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	8.659m	39.486ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	23.546m	66.361ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
		alert_handler_tl_intg_err	1.992m	15.563ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.992m	15.563ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	8.659m	39.486ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.655m	4.679ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.655m	4.679ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.655m	4.679ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.655m	4.679ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.262m	3.022ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	53.193m	225.768ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.262m	3.022ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.487m	256.000ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.487m	256.000ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	39.710s	1.201ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	10.992m	24.126ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			831	850	97.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.21	99.99	98.69	97.09	100.00	100.00	99.38	99.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
- Test alert_handler_stress_all_with_rand_reset has 16 failures.
  - 1.alert_handler_stress_all_with_rand_reset.85767190045019515113857114593779612473607001874549829740586536900019569262352
    Line 5282, in log /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7370382935 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7370382935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.alert_handler_stress_all_with_rand_reset.95900377920589819194388738732482455889335477988877226563489963564333010384706
    Line 1125, in log /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1645513270 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1645513270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
Job timed out after * minutes has 2 failures:
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 0.alert_handler_lpg_stub_clk.18096730618967718340657295776598299153554523705992112469803998350335093773773
    Log /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
- Test alert_handler_lpg has 1 failures.
  - 46.alert_handler_lpg.58658720075203504869505075242641673187092787668442269254407204770119543882084
    Log /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/46.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 12.alert_handler_stress_all.21847195859499199330331128660944935235376165467021693482451004598571801490414
    Line 99796, in log /workspaces/repo/scratch/os_regression_2024_08_26/alert_handler-sim-vcs/12.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 66977866301 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 66977866301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4674f625b3`