a861deb3de| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 1.759m | 1.290ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 14.980s | 481.046us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 14.370s | 128.596us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 8.871m | 7.892ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 5.291m | 3.944ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 21.210s | 159.432us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 14.370s | 128.596us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 5.291m | 3.944ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 7.575m | 5.505ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 1.367m | 1.981ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 58.840m | 217.100ms | 48 | 50 | 96.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 1.365m | 1.121ms | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 1.759m | 1.290ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.630m | 1.120ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 1.806m | 2.338ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 12.640m | 52.762ms | 50 | 50 | 100.00 |
| V2 | lpg | alert_handler_lpg | 56.489m | 48.851ms | 49 | 50 | 98.00 |
| alert_handler_lpg_stub_clk | 53.352m | 38.043ms | 49 | 50 | 98.00 | ||
| V2 | stress_all | alert_handler_stress_all | 1.234h | 811.950ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 1.580m | 9.525ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 6.190s | 165.378us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 3.230s | 24.144us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 43.760s | 2.250ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 43.760s | 2.250ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 14.980s | 481.046us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 14.370s | 128.596us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 5.291m | 3.944ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 1.166m | 2.882ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 14.980s | 481.046us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 14.370s | 128.596us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 5.291m | 3.944ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 1.166m | 2.882ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 624 | 630 | 99.05 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 7.529m | 5.974ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 7.529m | 5.974ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 7.529m | 5.974ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 7.529m | 5.974ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 21.470m | 27.464ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 2.275m | 4.977ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 2.275m | 4.977ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 7.529m | 5.974ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 1.759m | 1.290ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 1.759m | 1.290ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 1.759m | 1.290ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 1.759m | 1.290ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 1.365m | 1.121ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 56.489m | 48.851ms | 49 | 50 | 98.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 1.365m | 1.121ms | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 58.840m | 217.100ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 58.840m | 217.100ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 37.350s | 941.912us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 12.165m | 20.493ms | 31 | 50 | 62.00 |
| V3 | TOTAL | 31 | 50 | 62.00 | |||
| TOTAL | 825 | 850 | 97.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 10 | 66.67 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.24 | 99.99 | 98.67 | 97.09 | 100.00 | 100.00 | 99.38 | 99.52 |
UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
3.alert_handler_stress_all_with_rand_reset.23446296869797588200986901523070036403481758467715545555414463075711732535835
Line 180, in log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 104654552 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 104654552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.alert_handler_stress_all_with_rand_reset.69679488386572633811896738087299514491726854785183471198740722309767135571292
Line 12570, in log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 35317920911 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 35317920911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
Job timed out after * minutes has 4 failures:
Test alert_handler_entropy has 2 failures.
0.alert_handler_entropy.33038937254404711102632776528819013052563839724378174484739364397945981804236
Log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_entropy/latest/run.log
Job timed out after 60 minutes
16.alert_handler_entropy.50002354333631925839010178413613679859458985721539861217820975941571391000122
Log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_entropy/latest/run.log
Job timed out after 60 minutes
Test alert_handler_lpg_stub_clk has 1 failures.
23.alert_handler_lpg_stub_clk.94114592562838796610752721807235172647751644214116985318323306277494612106273
Log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest/run.log
Job timed out after 60 minutes
Test alert_handler_lpg has 1 failures.
45.alert_handler_lpg.36203078303209000898577429931596615162148222819048227147696550615285791173341
Log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_lpg/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:
5.alert_handler_stress_all.88343292221924462893725656968837535764498459539745826755461850847008911474226
Line 74467, in log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 36421465826 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 6 [0x6]) reg name: alert_handler_reg_block.classc_state
UVM_INFO @ 36421465826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
20.alert_handler_sig_int_fail.8484313270223234170222101057759290670895008703163700705405287307030453781235
Line 724, in log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 326414785 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 326414785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
41.alert_handler_stress_all_with_rand_reset.41354191568362823290145409366425516808656553604722546435078959741771511113164
Line 2324, in log /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1456957037 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1456957037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---