ALERT_HANDLER Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.835m	4.703ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.590s	66.213us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	16.400s	469.946us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	14.364m	47.386ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.540m	5.296ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	23.690s	390.657us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	16.400s	469.946us	20	20	100.00
		alert_handler_csr_aliasing	4.540m	5.296ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	8.127m	5.515ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.787m	4.597ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.405m	399.148ms	47	50	94.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.636m	1.045ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.835m	4.703ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.839m	5.504ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.731m	11.316ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	13.404m	14.962ms	50	50	100.00
V2	lpg	alert_handler_lpg	56.628m	70.524ms	47	50	94.00
		alert_handler_lpg_stub_clk	58.334m	204.642ms	48	50	96.00
V2	stress_all	alert_handler_stress_all	1.200h	65.271ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.415m	1.253ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	6.790s	44.842us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.700s	13.856us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	39.660s	1.673ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	39.660s	1.673ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.590s	66.213us	5	5	100.00
		alert_handler_csr_rw	16.400s	469.946us	20	20	100.00
		alert_handler_csr_aliasing	4.540m	5.296ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.347m	2.768ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.590s	66.213us	5	5	100.00
		alert_handler_csr_rw	16.400s	469.946us	20	20	100.00
		alert_handler_csr_aliasing	4.540m	5.296ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.347m	2.768ms	20	20	100.00
V2		TOTAL			618	630	98.10
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	9.514m	22.420ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	9.514m	22.420ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	9.514m	22.420ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	9.514m	22.420ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	23.382m	16.851ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
		alert_handler_tl_intg_err	1.722m	930.282us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.722m	930.282us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	9.514m	22.420ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.835m	4.703ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.835m	4.703ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.835m	4.703ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.835m	4.703ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.636m	1.045ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	56.628m	70.524ms	47	50	94.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.636m	1.045ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.405m	399.148ms	47	50	94.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.405m	399.148ms	47	50	94.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.147m	1.874ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	12.832m	23.185ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			823	850	96.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	10	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.62	99.99	98.69	92.65	100.00	100.00	99.38	99.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test alert_handler_stress_all_with_rand_reset has 13 failures.
  - 0.alert_handler_stress_all_with_rand_reset.47133143828429615541921689163779587637791284416884166567214430176253739677817
    Line 4087, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3243168234 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3243168234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.alert_handler_stress_all_with_rand_reset.24665591419184334947736932853522271901919532049808113424876461615402971392079
    Line 911, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 695900371 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 695900371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
Job timed out after * minutes has 8 failures:
- Test alert_handler_lpg has 3 failures.
  - 1.alert_handler_lpg.1501300181201636906266450013242022402834536268595083546076277158082245020124
    Log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/1.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```
  - 31.alert_handler_lpg.2042438941001787233325501578735084441026733268622722932762009216640572184149
    Log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test alert_handler_entropy has 3 failures.
  - 7.alert_handler_entropy.69941175427097152206783042706910259418559094780045514269463847823977626856456
    Log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/7.alert_handler_entropy/latest/run.log
```
  Job timed out after 60 minutes
```
  - 15.alert_handler_entropy.55067080629133673813453850874131496645241722177899942263775927514604366824341
    Log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/15.alert_handler_entropy/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test alert_handler_lpg_stub_clk has 2 failures.
  - 13.alert_handler_lpg_stub_clk.115268156286773241383948068588470124177197498845328985602442014320656238405421
    Log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
  - 31.alert_handler_lpg_stub_clk.10998728781176428142647364287928164329025133654760924974507712296572904210137
    Log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test alert_handler_stress_all_with_rand_reset has 2 failures.
  - 39.alert_handler_stress_all_with_rand_reset.108399585587551069806981476944078295284182875678235427608354331486465781799103
    Line 643, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2975018892 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2975018892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.alert_handler_stress_all_with_rand_reset.21946120376050784845762205777169177300850086112026365962426205138433947607860
    Line 396, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2670553051 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2670553051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 6.alert_handler_stress_all.1019134269178963854678595098559505985717153977505911203748347891841529798981
    Line 69202, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/6.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 138034529240 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 138034529240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* has 1 failures:
- Test alert_handler_stress_all has 1 failures.
  - 20.alert_handler_stress_all.115079868611537864978731341591984564523347370370528698671291878546239491970687
    Line 230, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/20.alert_handler_stress_all/latest/run.log
```
  UVM_ERROR @ 455480258 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: alert_handler_reg_block.loc_alert_cause_3
  UVM_INFO @ 455480258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 22.alert_handler_sig_int_fail.15536758392819663945929901748480969407959312578851317311963821340844660056551
    Line 315, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 581274665 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (9 [0x9] vs 401 [0x191])
  UVM_INFO @ 581274665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_b, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
- Test alert_handler_sig_int_fail has 1 failures.
  - 30.alert_handler_sig_int_fail.67714858737502087618005691584542387296303325296417894249257898149572452209959
    Line 396, in log /workspaces/repo/scratch/os_regression_2024_08_31/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest/run.log
```
  UVM_ERROR @ 246311770 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_b, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 246311770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`