ALERT_HANDLER Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.507m	1.109ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.730s	554.126us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	15.370s	198.219us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.762m	1.710ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.947m	4.868ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	18.160s	566.353us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	15.370s	198.219us	20	20	100.00
		alert_handler_csr_aliasing	5.947m	4.868ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.787m	5.175ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.584m	1.093ms	50	50	100.00
V2	entropy	alert_handler_entropy	52.982m	502.293ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.472m	9.110ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.507m	1.109ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.658m	2.279ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.773m	4.538ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	13.674m	27.279ms	49	50	98.00
V2	lpg	alert_handler_lpg	57.751m	59.161ms	49	50	98.00
		alert_handler_lpg_stub_clk	55.327m	60.709ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.331h	346.721ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.172m	4.277ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	6.170s	48.419us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.940s	38.202us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	33.760s	1.315ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	33.760s	1.315ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.730s	554.126us	5	5	100.00
		alert_handler_csr_rw	15.370s	198.219us	20	20	100.00
		alert_handler_csr_aliasing	5.947m	4.868ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.317m	2.520ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.730s	554.126us	5	5	100.00
		alert_handler_csr_rw	15.370s	198.219us	20	20	100.00
		alert_handler_csr_aliasing	5.947m	4.868ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.317m	2.520ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.593m	5.843ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.593m	5.843ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.593m	5.843ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.593m	5.843ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.068m	14.895ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
		alert_handler_tl_intg_err	2.303m	1.309ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	2.303m	1.309ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.593m	5.843ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.507m	1.109ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.507m	1.109ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.507m	1.109ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.507m	1.109ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.472m	9.110ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	57.751m	59.161ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.472m	9.110ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	52.982m	502.293ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	52.982m	502.293ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	49.520s	1.377ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.144m	23.432ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			825	850	97.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.99	98.71	97.09	100.00	100.00	99.38	99.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test alert_handler_stress_all_with_rand_reset has 21 failures.
  - 0.alert_handler_stress_all_with_rand_reset.46168791507196356013772172091131045390011723341337934017180471255454992164035
    Line 1971, in log /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1835598208 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1835598208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.alert_handler_stress_all_with_rand_reset.98007723343051859539397545331795885958330064756586741800466728112571043832108
    Line 4189, in log /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13880556231 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13880556231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
Job timed out after * minutes has 2 failures:
- Test alert_handler_lpg has 1 failures.
  - 2.alert_handler_lpg.65488401249183842502146238359474186676812146125264407444208932190457015825432
    Log /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```
- Test alert_handler_entropy has 1 failures.
  - 9.alert_handler_entropy.40372272904047936166389028004680921504823551132827724434500201729021595757277
    Log /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_entropy/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_esc_cnt has 1 failures:
- Test alert_handler_ping_timeout has 1 failures.
  - 11.alert_handler_ping_timeout.56271264164005558260115525042834532956022823843981308526814141561070614085514
    Line 317, in log /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest/run.log
```
  UVM_ERROR @ 765631585 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (103 [0x67] vs 196 [0xc4]) reg name: alert_handler_reg_block.classa_esc_cnt
  UVM_INFO @ 765631585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test alert_handler_stress_all_with_rand_reset has 1 failures.
  - 40.alert_handler_stress_all_with_rand_reset.55445470752715152305296038338950391483937062439469241445177278081876726878556
    Line 6184, in log /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1541176053 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1541176053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ALERT_HANDLER Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`