ALERT_HANDLER Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.429m	8.372ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	13.730s	128.149us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	14.710s	472.434us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	3.789m	11.880ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.441m	13.729ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	19.850s	614.112us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	14.710s	472.434us	20	20	100.00
		alert_handler_csr_aliasing	4.441m	13.729ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	7.468m	10.743ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.787m	7.615ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.874m	49.202ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.627m	4.528ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.429m	8.372ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.451m	3.642ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.760m	4.097ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.693m	56.512ms	49	50	98.00
V2	lpg	alert_handler_lpg	52.334m	51.689ms	50	50	100.00
		alert_handler_lpg_stub_clk	53.649m	50.718ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.078h	70.449ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	2.391m	4.851ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	6.320s	46.134us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.680s	11.382us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	39.900s	1.492ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	39.900s	1.492ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	13.730s	128.149us	5	5	100.00
		alert_handler_csr_rw	14.710s	472.434us	20	20	100.00
		alert_handler_csr_aliasing	4.441m	13.729ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.980s	538.691us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	13.730s	128.149us	5	5	100.00
		alert_handler_csr_rw	14.710s	472.434us	20	20	100.00
		alert_handler_csr_aliasing	4.441m	13.729ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.980s	538.691us	20	20	100.00
V2		TOTAL			628	630	99.68
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.481m	20.245ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.481m	20.245ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.481m	20.245ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.481m	20.245ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.134m	51.275ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
		alert_handler_tl_intg_err	2.169m	2.607ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	2.169m	2.607ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.481m	20.245ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.429m	8.372ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.429m	8.372ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.429m	8.372ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.429m	8.372ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.627m	4.528ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	52.334m	51.689ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.627m	4.528ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.874m	49.202ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.874m	49.202ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.030m	1.128ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.737m	38.140ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			835	850	98.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	99.99	98.72	97.09	100.00	100.00	99.38	99.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:

  • Test alert_handler_stress_all_with_rand_reset has 13 failures.

    • 8.alert_handler_stress_all_with_rand_reset.29743745092259707994004674267493621734892409281372598535109007479075716277790
      Line 2782, in log /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11520528203 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11520528203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.alert_handler_stress_all_with_rand_reset.59030875660485882892223278844596648597966155577946589388900911973152107809842
      Line 234, in log /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 218700395 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 218700395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_state has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 6.alert_handler_ping_timeout.96463421082585186280866952328921066527254743005634502145423212516898533746118
      Line 318, in log /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 2972266656 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 6 [0x6]) reg name: alert_handler_reg_block.classd_state
        UVM_INFO @ 2972266656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_esc_cnt has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 12.alert_handler_sig_int_fail.86199650203887661033871467168694429264661855441877306815330709237325339977918
      Line 395, in log /workspaces/repo/scratch/os_regression_2024_09_08/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @  59325697 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (115 [0x73] vs 22 [0x16]) reg name: alert_handler_reg_block.classa_esc_cnt
        UVM_INFO @  59325697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.09.05_04.25.32
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• 2024.08.29_23.17.16
• 2024.08.28_07.00.44
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