ALERT_HANDLER Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.618m	1.109ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	14.940s	488.549us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	14.350s	652.668us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.088m	5.948ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.203m	4.219ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	17.180s	595.050us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	14.350s	652.668us	20	20	100.00
		alert_handler_csr_aliasing	3.203m	4.219ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.139m	15.593ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.459m	943.546us	50	50	100.00
V2	entropy	alert_handler_entropy	58.167m	753.151ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.491m	1.882ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.618m	1.109ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.629m	2.535ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.720m	1.240ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.927m	17.561ms	50	50	100.00
V2	lpg	alert_handler_lpg	55.038m	114.263ms	48	50	96.00
		alert_handler_lpg_stub_clk	52.771m	291.639ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.216h	216.528ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.168m	8.540ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	7.080s	101.053us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.620s	21.072us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	28.620s	309.205us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	28.620s	309.205us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	14.940s	488.549us	5	5	100.00
		alert_handler_csr_rw	14.350s	652.668us	20	20	100.00
		alert_handler_csr_aliasing	3.203m	4.219ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.099m	635.903us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	14.940s	488.549us	5	5	100.00
		alert_handler_csr_rw	14.350s	652.668us	20	20	100.00
		alert_handler_csr_aliasing	3.203m	4.219ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.099m	635.903us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.013m	7.819ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.013m	7.819ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.013m	7.819ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.013m	7.819ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.467m	68.693ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
		alert_handler_tl_intg_err	1.720m	4.921ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.720m	4.921ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.013m	7.819ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.618m	1.109ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.618m	1.109ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.618m	1.109ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.618m	1.109ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.491m	1.882ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	55.038m	114.263ms	48	50	96.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.491m	1.882ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	58.167m	753.151ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	58.167m	753.151ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	36.540s	1.848ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	11.744m	5.801ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			824	850	96.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.21	99.99	98.67	97.09	100.00	100.00	99.38	99.36

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test alert_handler_stress_all_with_rand_reset has 23 failures.

    • 0.alert_handler_stress_all_with_rand_reset.18137979686981816185963745331834548458267149258524783136977723204819995319674
      Line 315, in log /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 221392206 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 221392206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_stress_all_with_rand_reset.22748233134716890870095899910131467123087070099446428441960095288953861318616
      Line 2723, in log /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1850161780 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1850161780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

• Job timed out after * minutes has 3 failures:

  • Test alert_handler_lpg has 2 failures.

    • 4.alert_handler_lpg.79002340824950069279992197178188223173758603060468774474746295488772716465486
      Log /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/4.alert_handler_lpg/latest/run.log

        Job timed out after 60 minutes
      

    • 17.alert_handler_lpg.40746604124529678385880018496071837229572756234923350586218347530479670826082
      Log /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/17.alert_handler_lpg/latest/run.log

        Job timed out after 60 minutes
      

  • Test alert_handler_lpg_stub_clk has 1 failures.

    • 22.alert_handler_lpg_stub_clk.38163323040373500685078910666702875631437422245191665873713814918472879032172
      Log /workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest/run.log

        Job timed out after 60 minutes
      

Past Results

• Latest
• lint
• 2024.09.10_08.15.52
• 2024.09.05_04.25.32
• 2024.09.02_11.35.09
• 2024.08.29_23.17.16
• 2024.08.28_07.00.44
• 2024.08.26_02.22.22