ADC_CTRL Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	16.180s	5.855ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.000s	1.069ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.080s	556.281us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	4.126m	51.016ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.840s	1.254ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.180s	552.169us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.080s	556.281us	20	20	100.00
		adc_ctrl_csr_aliasing	5.840s	1.254ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.445m	490.260ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.141m	489.690ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.103m	492.976ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	19.536m	492.294ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.682m	488.939ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	19.989m	496.867ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	19.916m	495.650ms	50	50	100.00
V2	clock_gating	adc_ctrl_clock_gating	20.660m	496.830ms	50	50	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	13.500s	5.149ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.682m	41.878ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	10.939m	117.236ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.584m	431.801ms	46	50	92.00
V2	alert_test	adc_ctrl_alert_test	1.870s	507.292us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.910s	510.652us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.650s	505.676us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.650s	505.676us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.000s	1.069ms	5	5	100.00
		adc_ctrl_csr_rw	2.080s	556.281us	20	20	100.00
		adc_ctrl_csr_aliasing	5.840s	1.254ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.880s	4.977ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.000s	1.069ms	5	5	100.00
		adc_ctrl_csr_rw	2.080s	556.281us	20	20	100.00
		adc_ctrl_csr_aliasing	5.840s	1.254ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	11.880s	4.977ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	tl_intg_err	adc_ctrl_sec_cm	19.970s	8.135ms	5	5	100.00
		adc_ctrl_tl_intg_err	22.910s	8.500ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.910s	8.500ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	11.656m	803.702ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			891	920	96.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	99.01	95.70	100.00	100.00	98.18	98.64	91.62

Failure Buckets

Offending '(wakeup_time == cfg_wakeup_time)' has 23 failures:
- Test adc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.adc_ctrl_stress_all_with_rand_reset.1594060714
    Line 334, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 10446049847 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 10446049847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.adc_ctrl_stress_all_with_rand_reset.837114840
    Line 420, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(wakeup_time == cfg_wakeup_time)'
  UVM_ERROR @ 81084719664 ps: (tb.sv:256) [ASSERT FAILED] WakeupTime_A
  UVM_INFO @ 81084719664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 21 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:400) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state

has 6 failures:

Test adc_ctrl_stress_all has 4 failures.

14.adc_ctrl_stress_all.1637433255
Line 404, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/14.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 350462983556 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 350462983556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.adc_ctrl_stress_all.2100291871
Line 327, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/16.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 335107014375 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 335107014375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test adc_ctrl_stress_all_with_rand_reset has 2 failures.

23.adc_ctrl_stress_all_with_rand_reset.2465338055
Line 335, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/23.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 290440159896 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 290440159896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.adc_ctrl_stress_all_with_rand_reset.3194427431
Line 484, in log /container/opentitan-public/scratch/os_regression/adc_ctrl-sim-vcs/26.adc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 584942639500 ps: (adc_ctrl_scoreboard.sv:400) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 584942639500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---