AES/MASKED Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	187.998us	1	1	100.00
V1	smoke	aes_smoke	12.000s	352.966us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	56.439us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	59.163us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	666.556us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	653.266us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	69.970us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	59.163us	20	20	100.00
		aes_csr_aliasing	5.000s	653.266us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	352.966us	50	50	100.00
		aes_config_error	24.000s	752.488us	50	50	100.00
		aes_stress	3.417m	2.636ms	50	50	100.00
V2	key_length	aes_smoke	12.000s	352.966us	50	50	100.00
		aes_config_error	24.000s	752.488us	50	50	100.00
		aes_stress	3.417m	2.636ms	50	50	100.00
V2	back2back	aes_stress	3.417m	2.636ms	50	50	100.00
		aes_b2b	41.000s	552.775us	50	50	100.00
V2	backpressure	aes_stress	3.417m	2.636ms	50	50	100.00
V2	multi_message	aes_smoke	12.000s	352.966us	50	50	100.00
		aes_config_error	24.000s	752.488us	50	50	100.00
		aes_stress	3.417m	2.636ms	50	50	100.00
		aes_alert_reset	22.000s	1.532ms	49	50	98.00
V2	failure_test	aes_config_error	24.000s	752.488us	50	50	100.00
		aes_alert_reset	22.000s	1.532ms	49	50	98.00
		aes_man_cfg_err	6.000s	82.432us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.500m	5.120ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	185.933us	1	1	100.00
V2	reset_recovery	aes_alert_reset	22.000s	1.532ms	49	50	98.00
V2	stress	aes_stress	3.417m	2.636ms	50	50	100.00
V2	sideload	aes_stress	3.417m	2.636ms	50	50	100.00
		aes_sideload	11.000s	296.629us	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	301.218us	50	50	100.00
V2	alert_test	aes_alert_test	7.000s	346.047us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	236.805us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	236.805us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	56.439us	5	5	100.00
		aes_csr_rw	4.000s	59.163us	20	20	100.00
		aes_csr_aliasing	5.000s	653.266us	5	5	100.00
		aes_same_csr_outstanding	4.000s	105.871us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	56.439us	5	5	100.00
		aes_csr_rw	4.000s	59.163us	20	20	100.00
		aes_csr_aliasing	5.000s	653.266us	5	5	100.00
		aes_same_csr_outstanding	4.000s	105.871us	20	20	100.00
V2		TOTAL			490	491	99.80
V2S	reseeding	aes_reseed	5.050m	3.828ms	50	50	100.00
V2S	fault_inject	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	76.882us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	76.882us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	76.882us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	76.882us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	467.346us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	3.256ms	5	5	100.00
		aes_tl_intg_err	5.000s	130.402us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	130.402us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	22.000s	1.532ms	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	76.882us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	352.966us	50	50	100.00
		aes_stress	3.417m	2.636ms	50	50	100.00
		aes_alert_reset	22.000s	1.532ms	49	50	98.00
		aes_core_fi	1.617m	10.057ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	76.882us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_stress	3.417m	2.636ms	50	50	100.00
		aes_readability	5.000s	142.618us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	3.417m	2.636ms	50	50	100.00
		aes_sideload	11.000s	296.629us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	142.618us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	142.618us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	142.618us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	142.618us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	142.618us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.417m	2.636ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	3.417m	2.636ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	33.117m	200.000ms	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
		aes_ctr_fi	7.000s	246.772us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	33.117m	200.000ms	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	54.000s	10.121ms	336	350	96.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	33.117m	200.000ms	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_ctr_fi	7.000s	246.772us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
		aes_ctr_fi	7.000s	246.772us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	22.000s	1.532ms	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
		aes_ctr_fi	7.000s	246.772us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
		aes_ctr_fi	7.000s	246.772us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_ctr_fi	7.000s	246.772us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	33.117m	200.000ms	48	50	96.00
		aes_control_fi	34.000s	10.007ms	284	300	94.67
		aes_cipher_fi	54.000s	10.121ms	336	350	96.00
V2S		TOTAL			949	985	96.35
V3		TOTAL			0	0	--
		TOTAL			1545	1582	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	12	12	11	91.67
V2S	11	11	6	54.55

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.46	99.01	97.53	99.41	95.81	95.60	97.78	98.67	92.29

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test aes_control_fi has 9 failures.
  - 32.aes_control_fi.891202993
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job ID: smart:9ae799fb-d5a9-40fe-85c5-0a108f6c259e
```
  - 66.aes_control_fi.1560275058
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/66.aes_control_fi/latest/run.log
```
  Job ID: smart:5483d477-f035-473a-9946-62f47dc9ca8e
```
  - ... and 7 more failures.
- Test aes_ctr_fi has 1 failures.
  - 32.aes_ctr_fi.1565440972
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/32.aes_ctr_fi/latest/run.log
```
  Job ID: smart:98b7476c-d0ed-4b6b-a127-4b8d2bfdee2e
```
- Test aes_cipher_fi has 4 failures.
  - 96.aes_cipher_fi.1820455797
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ea1b95d6-63f4-49ba-99bc-ebe64e16e9f3
```
  - 107.aes_cipher_fi.2192958714
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/107.aes_cipher_fi/latest/run.log
```
  Job ID: smart:104def43-8f11-48a0-9eeb-68e038356c0d
```
  - ... and 2 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:

Test aes_cipher_fi has 10 failures.

5.aes_cipher_fi.2926110905
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10009864117 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009864117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.aes_cipher_fi.1478966444
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log

  UVM_FATAL @ 10009739294 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009739294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:

Test aes_control_fi has 7 failures.

6.aes_control_fi.1357730574
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log

  UVM_FATAL @ 10019036373 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019036373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

53.aes_control_fi.585465251
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/53.aes_control_fi/latest/run.log

  UVM_FATAL @ 10009624178 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009624178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:

Test aes_core_fi has 3 failures.

2.aes_core_fi.2436699996
Line 281, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log

  UVM_FATAL @ 10003735763 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003735763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aes_core_fi.2160330786
Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/47.aes_core_fi/latest/run.log

  UVM_FATAL @ 10056860368 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10056860368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:

Test aes_fi has 1 failures.

11.aes_fi.77963084
Line 10509, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_fi/latest/run.log

  UVM_FATAL @  72329506 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  72329506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_fi has 1 failures.
  - 24.aes_fi.2431383597
    Line 9386183, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,984): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

25.aes_alert_reset.1046021307
Line 2344, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/25.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 9412915 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9402915 PS)
  UVM_ERROR @   9412915 ps: (aes_core.sv:984) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   9412915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---