AES/MASKED Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	81.024us	1	1	100.00
V1	smoke	aes_smoke	11.000s	392.476us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	18.000s	79.708us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	61.240us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.426ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	69.725us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	75.727us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	61.240us	20	20	100.00
		aes_csr_aliasing	8.000s	69.725us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	392.476us	50	50	100.00
		aes_config_error	35.000s	1.731ms	50	50	100.00
		aes_stress	51.000s	2.539ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	392.476us	50	50	100.00
		aes_config_error	35.000s	1.731ms	50	50	100.00
		aes_stress	51.000s	2.539ms	50	50	100.00
V2	back2back	aes_stress	51.000s	2.539ms	50	50	100.00
		aes_b2b	46.000s	563.819us	50	50	100.00
V2	backpressure	aes_stress	51.000s	2.539ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	392.476us	50	50	100.00
		aes_config_error	35.000s	1.731ms	50	50	100.00
		aes_stress	51.000s	2.539ms	50	50	100.00
		aes_alert_reset	17.000s	1.008ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	12.000s	331.692us	50	50	100.00
		aes_config_error	35.000s	1.731ms	50	50	100.00
		aes_alert_reset	17.000s	1.008ms	50	50	100.00
V2	trigger_clear_test	aes_clear	39.000s	18.142ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	287.788us	1	1	100.00
V2	reset_recovery	aes_alert_reset	17.000s	1.008ms	50	50	100.00
V2	stress	aes_stress	51.000s	2.539ms	50	50	100.00
V2	sideload	aes_stress	51.000s	2.539ms	50	50	100.00
		aes_sideload	24.000s	1.887ms	50	50	100.00
V2	deinitialization	aes_deinit	1.100m	1.840ms	50	50	100.00
V2	stress_all	aes_stress_all	1.050m	8.153ms	9	10	90.00
V2	alert_test	aes_alert_test	7.000s	65.730us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	176.439us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	176.439us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	18.000s	79.708us	5	5	100.00
		aes_csr_rw	8.000s	61.240us	20	20	100.00
		aes_csr_aliasing	8.000s	69.725us	5	5	100.00
		aes_same_csr_outstanding	10.000s	72.921us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	18.000s	79.708us	5	5	100.00
		aes_csr_rw	8.000s	61.240us	20	20	100.00
		aes_csr_aliasing	8.000s	69.725us	5	5	100.00
		aes_same_csr_outstanding	10.000s	72.921us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.683m	3.741ms	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	103.977us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	103.977us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	103.977us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	103.977us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	279.820us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	842.193us	5	5	100.00
		aes_tl_intg_err	10.000s	222.051us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	222.051us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	17.000s	1.008ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	103.977us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	392.476us	50	50	100.00
		aes_stress	51.000s	2.539ms	50	50	100.00
		aes_alert_reset	17.000s	1.008ms	50	50	100.00
		aes_core_fi	1.550m	10.007ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	103.977us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	26.000s	1.343ms	50	50	100.00
		aes_stress	51.000s	2.539ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	51.000s	2.539ms	50	50	100.00
		aes_sideload	24.000s	1.887ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	26.000s	1.343ms	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	26.000s	1.343ms	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	26.000s	1.343ms	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	26.000s	1.343ms	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	26.000s	1.343ms	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	51.000s	2.539ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	51.000s	2.539ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	488.666us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
		aes_ctr_fi	7.000s	334.830us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	488.666us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.005ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	488.666us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_ctr_fi	7.000s	334.830us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
		aes_ctr_fi	7.000s	334.830us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	17.000s	1.008ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
		aes_ctr_fi	7.000s	334.830us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
		aes_ctr_fi	7.000s	334.830us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_ctr_fi	7.000s	334.830us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	488.666us	50	50	100.00
		aes_control_fi	45.000s	10.014ms	282	300	94.00
		aes_cipher_fi	48.000s	10.005ms	340	350	97.14
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.867m	7.284ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1560	1602	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.58	98.92	97.29	99.45	95.90	97.72	100.00	99.11	96.61

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
- Test aes_cipher_fi has 6 failures.
  - 4.aes_cipher_fi.58997928195759612969020517340615827907486512323262848243954064291294185983197
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0d0139be-9eaa-4243-90f8-13d903011fe2
```
  - 20.aes_cipher_fi.31037083125866420687261289695393533456968501855990779514848463298491294799860
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5bd7f846-7b74-4900-b57b-92c7a5c253f1
```
  - ... and 4 more failures.
- Test aes_control_fi has 12 failures.
  - 28.aes_control_fi.12466907680345724637487271154277865621437221293889109588300985735316021136581
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job ID: smart:52ae1ae7-fc36-448d-adfd-f5dd64de5a5d
```
  - 79.aes_control_fi.7933160391272862411720112689204968112336801101552708297539307839963805741035
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/79.aes_control_fi/latest/run.log
```
  Job ID: smart:b3565f61-93a6-45ef-beed-a555e4fefc7c
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

3.aes_stress_all_with_rand_reset.89240669051935551843694840746342563694250767028290324960647676368121967433752
Line 1010, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 663982421 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 663982421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.89374076532864693348535059299769456088423556624399890624396104379677553809019
Line 1739, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5073673518 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5073673518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 31.aes_control_fi.109228738590266817176590911954945712300682234052619477375397141777059461686315
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10063382865 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10063382865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 69.aes_control_fi.72611483122376835660454932280918268211643949030773618507369319542123126499616
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/69.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014153696 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014153696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 10.aes_cipher_fi.100598101245236659174160337627366431422337009449876582185170858003968848803489
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009314586 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009314586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 97.aes_cipher_fi.80464349314647934006041900924043868292278573054517012359744377364777910229560
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/97.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10030921887 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030921887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 35.aes_core_fi.18489045331951594076865812965836575148259172231089692795658710308225101271987
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009380253 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009380253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.aes_core_fi.35736622180465675680784026726172904379155952487585796599460015924438242626596
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007224292 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007224292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.62440350151561194861001764053365920674784137409473942632026614884144766509594
Line 757, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 562472852 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 562472852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aes_stress_all_with_rand_reset.55281914823795459542245409916432946814266273663323000319838911392244109763135
Line 779, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1351456158 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1351456158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.16602443657381959459917316061184220457305331300178390992785085133827952934789
    Line 346, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 413293584 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 413293584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_stress_all_with_rand_reset.25170493083075266002528492360225240982990796704902411360440821718813862029746
    Line 362, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1071466481 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1071466481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.38017447308649574813833869886573226598114618441010423664953979164984759227364
    Line 2159, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_ERROR @   8411371 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @   8411371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```