AES/MASKED Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	1.701ms	1	1	100.00
V1	smoke	aes_smoke	8.000s	748.215us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	179.541us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	73.138us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	450.340us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.833m	10.023ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	281.072us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	73.138us	20	20	100.00
		aes_csr_aliasing	5.833m	10.023ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	8.000s	748.215us	50	50	100.00
		aes_config_error	32.000s	996.888us	50	50	100.00
		aes_stress	9.000s	433.859us	50	50	100.00
V2	key_length	aes_smoke	8.000s	748.215us	50	50	100.00
		aes_config_error	32.000s	996.888us	50	50	100.00
		aes_stress	9.000s	433.859us	50	50	100.00
V2	back2back	aes_stress	9.000s	433.859us	50	50	100.00
		aes_b2b	44.000s	1.050ms	50	50	100.00
V2	backpressure	aes_stress	9.000s	433.859us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	748.215us	50	50	100.00
		aes_config_error	32.000s	996.888us	50	50	100.00
		aes_stress	9.000s	433.859us	50	50	100.00
		aes_alert_reset	15.000s	2.328ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	510.410us	50	50	100.00
		aes_config_error	32.000s	996.888us	50	50	100.00
		aes_alert_reset	15.000s	2.328ms	50	50	100.00
V2	trigger_clear_test	aes_clear	45.000s	3.273ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	434.709us	1	1	100.00
V2	reset_recovery	aes_alert_reset	15.000s	2.328ms	50	50	100.00
V2	stress	aes_stress	9.000s	433.859us	50	50	100.00
V2	sideload	aes_stress	9.000s	433.859us	50	50	100.00
		aes_sideload	11.000s	159.711us	50	50	100.00
V2	deinitialization	aes_deinit	48.000s	1.799ms	50	50	100.00
V2	stress_all	aes_stress_all	1.767m	2.896ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	153.648us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	257.416us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	257.416us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	179.541us	5	5	100.00
		aes_csr_rw	3.000s	73.138us	20	20	100.00
		aes_csr_aliasing	5.833m	10.023ms	4	5	80.00
		aes_same_csr_outstanding	6.083m	10.016ms	18	20	90.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	179.541us	5	5	100.00
		aes_csr_rw	3.000s	73.138us	20	20	100.00
		aes_csr_aliasing	5.833m	10.023ms	4	5	80.00
		aes_same_csr_outstanding	6.083m	10.016ms	18	20	90.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	1.150m	4.280ms	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	64.442us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	64.442us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	64.442us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	64.442us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	454.142us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	1.700ms	5	5	100.00
		aes_tl_intg_err	5.000s	160.104us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	160.104us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	15.000s	2.328ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	64.442us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	748.215us	50	50	100.00
		aes_stress	9.000s	433.859us	50	50	100.00
		aes_alert_reset	15.000s	2.328ms	50	50	100.00
		aes_core_fi	1.600m	10.018ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	64.442us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	242.067us	50	50	100.00
		aes_stress	9.000s	433.859us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	433.859us	50	50	100.00
		aes_sideload	11.000s	159.711us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	242.067us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	242.067us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	242.067us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	242.067us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	242.067us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	433.859us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	433.859us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	796.989us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
		aes_ctr_fi	4.000s	72.631us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	796.989us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	10.012ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	796.989us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_ctr_fi	4.000s	72.631us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
		aes_ctr_fi	4.000s	72.631us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	15.000s	2.328ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
		aes_ctr_fi	4.000s	72.631us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
		aes_ctr_fi	4.000s	72.631us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_ctr_fi	4.000s	72.631us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	796.989us	49	50	98.00
		aes_control_fi	51.000s	10.004ms	270	300	90.00
		aes_cipher_fi	50.000s	10.012ms	337	350	96.29
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.450m	17.403ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1542	1602	96.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.58	98.92	97.29	99.45	95.97	97.72	100.00	98.96	96.81

Failure Buckets

Job aes_masked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 20 failures.
  - 5.aes_control_fi.49133349716362133562311294311741581048704947024782399310534989598602945747914
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:eda2dc1a-9594-41f3-9806-8a4b25765734
```
  - 21.aes_control_fi.12932134216444375863166591375466939156407308517272111091543698288519771723076
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job ID: smart:c2ac336c-ee2c-4ff6-b0be-1a579f8c0386
```
  - ... and 18 more failures.
- Test aes_cipher_fi has 9 failures.
  - 58.aes_cipher_fi.47203563387971454676796871845433099103050937070795233049501542410441744095762
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/58.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7abab14a-8b1b-41dd-8dd0-1b79d444cf95
```
  - 94.aes_cipher_fi.67693819599831441192933495625465040757894680924603644092559107545045464908162
    Log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/94.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0099496b-ed32-4941-af28-60866769f7ec
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 11.aes_control_fi.41350027873552452074581153051079892988188627864021193018940034449619594302080
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10044937506 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044937506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.aes_control_fi.48157249408564873480289620881408893489919917565778134804603935485675660794270
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012573260 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012573260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.70869906644568168641443393522765652073419566272599572780268238567709817131621
Line 1360, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2794424734 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2794424734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.39668149310371090306435613581353366205526562593650234324233848385077242906140
Line 436, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 988115694 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 988115694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 61.aes_cipher_fi.69377419621094334838581771805955523501821085721687262211354845673898569466898
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/61.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007611962 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007611962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 172.aes_cipher_fi.109482219799561746826042652077986013200522058101372910798813232069350060977283
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/172.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012111080 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012111080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.104148908224924487998182193647197098350898088596677402466851601064658010497778
Line 868, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 448944427 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 448944427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.4782274482484134557008840298455981304670870967696031789871893764537892576545
Line 922, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2827136314 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2827136314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 1.aes_same_csr_outstanding.95456403783110519192666099299978581975074510815831432042712663617103787541211
    Line 297, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/1.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10016427986 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xc376af84) == 0x0
  UVM_INFO @ 10016427986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_csr_aliasing has 1 failures.
  - 2.aes_csr_aliasing.57435270339636927045974111014363157476163295913694326389047354430824582980648
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/2.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10023116619 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x34e82684) == 0x0
  UVM_INFO @ 10023116619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 38.aes_core_fi.115697730596360263083833887590711981692284314174062729102246524049675082133965
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018077165 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018077165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_core_fi.110366236670502659822873041182541598793976902814533700021511922641432321137460
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008188936 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008188936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 16.aes_same_csr_outstanding.29579571270713874206735628408694753699130525665665684850620491667741929157088
    Line 295, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/16.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10018956375 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x129da384) == 0x0
  UVM_INFO @ 10018956375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 17.aes_fi.41873810098076298909308044018663314314118942311160805868912973513597645856500
    Line 12488, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/17.aes_fi/latest/run.log
```
  UVM_FATAL @  95771441 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  95771441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_ctr_fi has 1 failures.
  - 24.aes_ctr_fi.72675224651563157126912425804542153614342475656336403412729379753217322938739
    Line 309, in log /container/opentitan-public/scratch/os_regression/aes_masked-sim-xcelium/24.aes_ctr_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 11913218 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 11869740 PS)
  UVM_ERROR @  11913218 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  11913218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```