AES/MASKED Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: XCELIUM

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	53.589us	1	1	100.00
V1	smoke	aes_smoke	1.500m	102.927us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	29.000s	62.202us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.083m	55.592us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.067m	1.496ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	58.000s	90.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.483m	64.425us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.083m	55.592us	20	20	100.00
		aes_csr_aliasing	58.000s	90.899us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.500m	102.927us	50	50	100.00
		aes_config_error	1.600m	126.282us	50	50	100.00
		aes_stress	1.500m	79.713us	50	50	100.00
V2	key_length	aes_smoke	1.500m	102.927us	50	50	100.00
		aes_config_error	1.600m	126.282us	50	50	100.00
		aes_stress	1.500m	79.713us	50	50	100.00
V2	back2back	aes_stress	1.500m	79.713us	50	50	100.00
		aes_b2b	2.250m	773.579us	50	50	100.00
V2	backpressure	aes_stress	1.500m	79.713us	50	50	100.00
V2	multi_message	aes_smoke	1.500m	102.927us	50	50	100.00
		aes_config_error	1.600m	126.282us	50	50	100.00
		aes_stress	1.500m	79.713us	50	50	100.00
		aes_alert_reset	1.717m	136.740us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.767m	94.272us	50	50	100.00
		aes_config_error	1.600m	126.282us	50	50	100.00
		aes_alert_reset	1.717m	136.740us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.400m	5.484ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	17.000s	1.531ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.717m	136.740us	50	50	100.00
V2	stress	aes_stress	1.500m	79.713us	50	50	100.00
V2	sideload	aes_stress	1.500m	79.713us	50	50	100.00
		aes_sideload	1.550m	106.442us	50	50	100.00
V2	deinitialization	aes_deinit	1.550m	197.740us	50	50	100.00
V2	stress_all	aes_stress_all	1.250m	1.163ms	10	10	100.00
V2	alert_test	aes_alert_test	1.517m	128.852us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.500m	489.973us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.500m	489.973us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	29.000s	62.202us	5	5	100.00
		aes_csr_rw	1.083m	55.592us	20	20	100.00
		aes_csr_aliasing	58.000s	90.899us	5	5	100.00
		aes_same_csr_outstanding	1.117m	197.820us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	29.000s	62.202us	5	5	100.00
		aes_csr_rw	1.083m	55.592us	20	20	100.00
		aes_csr_aliasing	58.000s	90.899us	5	5	100.00
		aes_same_csr_outstanding	1.117m	197.820us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.917m	221.935us	50	50	100.00
V2S	fault_inject	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.083m	153.789us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.083m	153.789us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.083m	153.789us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.083m	153.789us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.433m	113.151us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.389ms	5	5	100.00
		aes_tl_intg_err	1.517m	172.421us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.517m	172.421us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.717m	136.740us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.083m	153.789us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.500m	102.927us	50	50	100.00
		aes_stress	1.500m	79.713us	50	50	100.00
		aes_alert_reset	1.717m	136.740us	50	50	100.00
		aes_core_fi	2.567m	10.013ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.083m	153.789us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.483m	59.783us	50	50	100.00
		aes_stress	1.500m	79.713us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.500m	79.713us	50	50	100.00
		aes_sideload	1.550m	106.442us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.483m	59.783us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.483m	59.783us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.483m	59.783us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.483m	59.783us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.483m	59.783us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.500m	79.713us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.500m	79.713us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.883m	6.220ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
		aes_ctr_fi	31.000s	77.885us	35	50	70.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.883m	6.220ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	102.824us	268	350	76.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.883m	6.220ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_ctr_fi	31.000s	77.885us	35	50	70.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
		aes_ctr_fi	31.000s	77.885us	35	50	70.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.717m	136.740us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
		aes_ctr_fi	31.000s	77.885us	35	50	70.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
		aes_ctr_fi	31.000s	77.885us	35	50	70.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_ctr_fi	31.000s	77.885us	35	50	70.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.883m	6.220ms	50	50	100.00
		aes_control_fi	57.000s	55.700us	222	300	74.00
		aes_cipher_fi	1.000m	102.824us	268	350	76.57
V2S		TOTAL			807	985	81.93
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	56.000s	1.905ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1414	1602	88.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.56	96.34	99.43	95.87	97.64	97.78	99.11	96.81

Failure Buckets

Job timed out after * minutes has 165 failures:
- Test aes_control_fi has 76 failures.
  - 12.aes_control_fi.108401893827681700282893809465556947001043161905222887549396197624359066981521
    Log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_control_fi.41531567112864372992187621389195321651733827618686134893337357348282576202413
    Log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 74 more failures.
- Test aes_cipher_fi has 74 failures.
  - 12.aes_cipher_fi.9351412627387848376564869481949153122416106147183209975950659804586046320008
    Log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_cipher_fi.102690892852951726609666136654256141547317901161334705247979467860126715057250
    Log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 72 more failures.
- Test aes_ctr_fi has 15 failures.
  - 12.aes_ctr_fi.89794391190237195025404394657765609269740215356819837486044364760186002788774
    Log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/12.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_ctr_fi.19532761029887266102902280106693911403275006849999628751179103638852356677579
    Log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 32.aes_cipher_fi.77105284407472243981746847321620211585670510064617254388183159029632798380427
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10027875613 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027875613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 92.aes_cipher_fi.55706327939675005011512873792639552774355109852624062877287188797318095422533
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/92.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009383336 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009383336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.80178196052995735508410850893682708201822415593711921567792715888281745543568
Line 616, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1363765387 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1363765387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.76130212557031517495073235978246680486262164207566210062889015331900489241967
Line 664, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2236315217 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2236315217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 8.aes_core_fi.39482624715897146431203917233077252463195828095594124834083823793653362226169
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006738374 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006738374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.aes_core_fi.109684145443230680572271827957840609789159425808066414373778261015859908886278
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/13.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013422544 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013422544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.69886990271058075911356149436174754583007263365240516373734297610836662531376
    Line 300, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2030563552 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2030563552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_stress_all_with_rand_reset.100004733357251700203892242572677318462911624856984701315041245802891441191895
    Line 419, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1022287839 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1022287839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 97.aes_control_fi.113848777874881981386539757102424464415807050144886325605176008925567821436119
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008499493 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008499493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 208.aes_control_fi.77291586337649640660316750788926812874349626587907389497135013267467725379512
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/208.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018461460 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018461460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.100562304062208955258859763179359920893696814320113940569835510725867446590172
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_08_26/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  95718520 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  95718520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```