AES/MASKED Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	39.000s	88.382us	1	1	100.00
V1	smoke	aes_smoke	1.950m	93.220us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	28.000s	65.463us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.567m	55.172us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	33.000s	203.027us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	33.000s	267.332us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.500m	72.442us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.567m	55.172us	20	20	100.00
		aes_csr_aliasing	33.000s	267.332us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.950m	93.220us	50	50	100.00
		aes_config_error	1.917m	217.407us	50	50	100.00
		aes_stress	1.967m	92.080us	50	50	100.00
V2	key_length	aes_smoke	1.950m	93.220us	50	50	100.00
		aes_config_error	1.917m	217.407us	50	50	100.00
		aes_stress	1.967m	92.080us	50	50	100.00
V2	back2back	aes_stress	1.967m	92.080us	50	50	100.00
		aes_b2b	1.833m	233.470us	50	50	100.00
V2	backpressure	aes_stress	1.967m	92.080us	50	50	100.00
V2	multi_message	aes_smoke	1.950m	93.220us	50	50	100.00
		aes_config_error	1.917m	217.407us	50	50	100.00
		aes_stress	1.967m	92.080us	50	50	100.00
		aes_alert_reset	2.000m	221.662us	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.083m	81.492us	50	50	100.00
		aes_config_error	1.917m	217.407us	50	50	100.00
		aes_alert_reset	2.000m	221.662us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.967m	5.107ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	47.000s	811.304us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000m	221.662us	50	50	100.00
V2	stress	aes_stress	1.967m	92.080us	50	50	100.00
V2	sideload	aes_stress	1.967m	92.080us	50	50	100.00
		aes_sideload	1.950m	57.544us	50	50	100.00
V2	deinitialization	aes_deinit	2.633m	72.690us	50	50	100.00
V2	stress_all	aes_stress_all	1.983m	338.924us	10	10	100.00
V2	alert_test	aes_alert_test	1.433m	69.407us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.650m	102.271us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.650m	102.271us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	28.000s	65.463us	5	5	100.00
		aes_csr_rw	1.567m	55.172us	20	20	100.00
		aes_csr_aliasing	33.000s	267.332us	5	5	100.00
		aes_same_csr_outstanding	1.550m	149.503us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	28.000s	65.463us	5	5	100.00
		aes_csr_rw	1.567m	55.172us	20	20	100.00
		aes_csr_aliasing	33.000s	267.332us	5	5	100.00
		aes_same_csr_outstanding	1.550m	149.503us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.233m	1.481ms	50	50	100.00
V2S	fault_inject	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.533m	61.403us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.533m	61.403us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.533m	61.403us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.533m	61.403us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.417m	116.731us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	56.000s	261.235us	5	5	100.00
		aes_tl_intg_err	1.600m	345.118us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.600m	345.118us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000m	221.662us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.533m	61.403us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.950m	93.220us	50	50	100.00
		aes_stress	1.967m	92.080us	50	50	100.00
		aes_alert_reset	2.000m	221.662us	50	50	100.00
		aes_core_fi	2.667m	78.753us	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.533m	61.403us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.967m	60.172us	50	50	100.00
		aes_stress	1.967m	92.080us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.967m	92.080us	50	50	100.00
		aes_sideload	1.950m	57.544us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.967m	60.172us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.967m	60.172us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.967m	60.172us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.967m	60.172us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.967m	60.172us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.967m	92.080us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.967m	92.080us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.667m	1.499ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
		aes_ctr_fi	1.000m	56.653us	39	50	78.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.667m	1.499ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	82.625us	270	350	77.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.667m	1.499ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_ctr_fi	1.000m	56.653us	39	50	78.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
		aes_ctr_fi	1.000m	56.653us	39	50	78.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000m	221.662us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
		aes_ctr_fi	1.000m	56.653us	39	50	78.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
		aes_ctr_fi	1.000m	56.653us	39	50	78.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_ctr_fi	1.000m	56.653us	39	50	78.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.667m	1.499ms	49	50	98.00
		aes_control_fi	1.000m	52.499us	227	300	75.67
		aes_cipher_fi	1.000m	82.625us	270	350	77.14
V2S		TOTAL			817	985	82.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.317m	1.243ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1424	1602	88.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.55	96.32	99.43	95.74	97.64	98.52	98.96	96.61

Failure Buckets

Job timed out after * minutes has 158 failures:
- Test aes_control_fi has 70 failures.
  - 4.aes_control_fi.3402737383417551951729854045609870429461689811090557928385230227565280834886
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 7.aes_control_fi.77615562823166946414133449520186320704678426517909718764743565939956188949911
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 68 more failures.
- Test aes_cipher_fi has 77 failures.
  - 10.aes_cipher_fi.24523053479287154013638405839967336290580412693751352707082478747903120019784
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_cipher_fi.87858735090707655589503922508403772687577365695212170752594340605962037762733
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 75 more failures.
- Test aes_ctr_fi has 11 failures.
  - 10.aes_ctr_fi.44786103807414226522686846565055055216257735245968884119494496127877534641424
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/10.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 12.aes_ctr_fi.84085892545799463459582464938093710840265894893151345031594196597771367486450
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/12.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.49587689820783486261748602073492746276600212767779937926528049029367371914475
Line 195, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  43325719 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  43325719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.85365940039584882817926013459723969747969127858206946258065691739057806967776
Line 1289, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1409561952 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1409561952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 31.aes_core_fi.13770988449088924420446600666691087784999201625462515666995729952905333806387
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035264446 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035264446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_core_fi.17076622032920658110302861793624709518800248641163751063566200414687546237872
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014346283 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014346283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 39.aes_control_fi.106324685192598489216575256318521566428435664741475913016246813954282873400507
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10030632732 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030632732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.aes_control_fi.23259767315489248102107993227034550284944256762563481033920793276202589619566
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014169893 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014169893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 148.aes_cipher_fi.68218493357582027293518913001197368685847366312433722351035421908858715917818
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/148.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022757891 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022757891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 214.aes_cipher_fi.78573227349268169912749321963577112837592671444019240197355339386522381266766
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/214.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009437248 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009437248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.11201826798386812399153106227466794921099839132844779847460886971447386164738
    Line 306, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 415999111 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 415999111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_stress_all_with_rand_reset.94822164466762230702599680805071222269083882914328939078498967775570213502930
    Line 386, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 187388067 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 187388067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

0.aes_fi.92559779930324302948174381394810595654257791083451087830078555457763475955584
Line 1530, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/0.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 4736381 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 4726381 PS)
  UVM_ERROR @   4736381 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   4736381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.67702743609435747025571550536032792274267027549005664975523917360427977004126
    Line 281, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 349527910 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 349527910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```