AES/MASKED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	85.493us	1	1	100.00
V1	smoke	aes_smoke	1.183m	166.642us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	31.000s	57.227us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.450m	88.603us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.567m	355.550us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.567m	315.679us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.250m	62.510us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.450m	88.603us	20	20	100.00
		aes_csr_aliasing	1.567m	315.679us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.183m	166.642us	50	50	100.00
		aes_config_error	1.250m	215.227us	50	50	100.00
		aes_stress	1.183m	59.041us	50	50	100.00
V2	key_length	aes_smoke	1.183m	166.642us	50	50	100.00
		aes_config_error	1.250m	215.227us	50	50	100.00
		aes_stress	1.183m	59.041us	50	50	100.00
V2	back2back	aes_stress	1.183m	59.041us	50	50	100.00
		aes_b2b	1.450m	272.854us	50	50	100.00
V2	backpressure	aes_stress	1.183m	59.041us	50	50	100.00
V2	multi_message	aes_smoke	1.183m	166.642us	50	50	100.00
		aes_config_error	1.250m	215.227us	50	50	100.00
		aes_stress	1.183m	59.041us	50	50	100.00
		aes_alert_reset	1.317m	70.992us	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.000m	62.020us	50	50	100.00
		aes_config_error	1.250m	215.227us	50	50	100.00
		aes_alert_reset	1.317m	70.992us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.283m	287.141us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	655.986us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.317m	70.992us	50	50	100.00
V2	stress	aes_stress	1.183m	59.041us	50	50	100.00
V2	sideload	aes_stress	1.183m	59.041us	50	50	100.00
		aes_sideload	1.717m	187.077us	50	50	100.00
V2	deinitialization	aes_deinit	1.117m	177.502us	50	50	100.00
V2	stress_all	aes_stress_all	2.317m	12.801ms	10	10	100.00
V2	alert_test	aes_alert_test	1.083m	57.086us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.533m	108.909us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.533m	108.909us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	31.000s	57.227us	5	5	100.00
		aes_csr_rw	1.450m	88.603us	20	20	100.00
		aes_csr_aliasing	1.567m	315.679us	5	5	100.00
		aes_same_csr_outstanding	1.467m	56.423us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	31.000s	57.227us	5	5	100.00
		aes_csr_rw	1.450m	88.603us	20	20	100.00
		aes_csr_aliasing	1.567m	315.679us	5	5	100.00
		aes_same_csr_outstanding	1.467m	56.423us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.783m	137.870us	50	50	100.00
V2S	fault_inject	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.133m	82.632us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.133m	82.632us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.133m	82.632us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.133m	82.632us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.533m	82.426us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.319ms	5	5	100.00
		aes_tl_intg_err	1.417m	410.003us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.417m	410.003us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.317m	70.992us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.133m	82.632us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.183m	166.642us	50	50	100.00
		aes_stress	1.183m	59.041us	50	50	100.00
		aes_alert_reset	1.317m	70.992us	50	50	100.00
		aes_core_fi	2.317m	10.065ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.133m	82.632us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.700m	347.386us	50	50	100.00
		aes_stress	1.183m	59.041us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.183m	59.041us	50	50	100.00
		aes_sideload	1.717m	187.077us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.700m	347.386us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.700m	347.386us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.700m	347.386us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.700m	347.386us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.700m	347.386us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.183m	59.041us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.183m	59.041us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.783m	347.009us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
		aes_ctr_fi	1.000m	84.796us	45	50	90.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.783m	347.009us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	58.066us	285	350	81.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.783m	347.009us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_ctr_fi	1.000m	84.796us	45	50	90.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
		aes_ctr_fi	1.000m	84.796us	45	50	90.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.317m	70.992us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
		aes_ctr_fi	1.000m	84.796us	45	50	90.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
		aes_ctr_fi	1.000m	84.796us	45	50	90.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_ctr_fi	1.000m	84.796us	45	50	90.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.783m	347.009us	49	50	98.00
		aes_control_fi	1.000m	76.819us	241	300	80.33
		aes_cipher_fi	1.017m	58.066us	285	350	81.43
V2S		TOTAL			851	985	86.40
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	44.000s	1.780ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1458	1602	91.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.30	99.44	95.76	97.72	97.78	99.11	96.21

Failure Buckets

Job timed out after * minutes has 120 failures:
- Test aes_control_fi has 55 failures.
  - 13.aes_control_fi.988442510247524855498907421799162917353977214774165545852022958069209629866
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 23.aes_control_fi.83290596586297972850868332373993531987891147351056352531229477239995752686655
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 53 more failures.
- Test aes_cipher_fi has 60 failures.
  - 13.aes_cipher_fi.14822958233401772942572682576040567450232657457494207803627936540340081029280
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 26.aes_cipher_fi.59695713871174905010033570603291708999524594307288807965600261886368827358876
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 58 more failures.
- Test aes_ctr_fi has 5 failures.
  - 24.aes_ctr_fi.72164461032026355766541200088450611646538829872877238839466815859444269762965
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/24.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_ctr_fi.43690209413060505597135943853435641127589116909456207867936963379576408457654
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/25.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.30118146413541087714423586797207783840800739384168618397297743093935651314455
Line 703, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 897392012 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 897392012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.79591862512579840718197890475618116815305316938792390048996245517859140697925
Line 597, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4041479710 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4041479710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 20.aes_cipher_fi.28209648665425620647082089562445200605549982447401339380352567963487652595508
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022014045 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022014045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_cipher_fi.71228112020703881104014416862849970178721439945466169594257206417177433025825
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/53.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10015710362 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015710362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 25.aes_control_fi.33133085948390140248993999104833597544200084983469918774678122331114779961280
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016813184 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016813184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.aes_control_fi.105212815075322311510162990278997977854572279459274784167658467704815675483201
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020679019 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020679019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 1.aes_core_fi.95544192901284299486510630965899788130001532663804485266466998352984734794960
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10041729651 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041729651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 64.aes_core_fi.74186762653424954902076166509068309758471979621314216099151820255324485653787
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013198395 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013198395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.50855221790994610846253059885884562021398936850998515399195085152703014234120
    Line 495, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3924618207 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 3924618207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_stress_all_with_rand_reset.60268397481704629042460183677989668192494641532241586028509328029575302209496
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  36575349 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  36575349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.18858752448617708797349700919383872640657678785489485874988658023767291517432
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 321621197 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 321621197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.91776185474102815674151551369367679601665369752959018874607259297693838483584
    Line 608, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2301738054 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2301738054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.80881213339350947363190230519463781162402329023759167240741027163509144387285
    Line 314, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 296889389 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 296889389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 41.aes_fi.113850527703542277004202245706413625937327115552131804533291836986976835842672
    Line 20231, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/41.aes_fi/latest/run.log
```
  UVM_FATAL @ 438072220 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 438072220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 67.aes_core_fi.93166361999352672987445785876038952181699370269432431062403548164629927287503
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_masked-sim-xcelium/67.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10065158476 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x17021a84, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10065158476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```