AES/MASKED Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	72.729us	1	1	100.00
V1	smoke	aes_smoke	1.617m	154.566us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	56.000s	78.527us	5	5	100.00
V1	csr_rw	aes_csr_rw	55.000s	64.248us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.000m	942.758us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	57.000s	372.364us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	55.000s	118.065us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	55.000s	64.248us	20	20	100.00
		aes_csr_aliasing	57.000s	372.364us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.617m	154.566us	50	50	100.00
		aes_config_error	1.350m	2.966ms	50	50	100.00
		aes_stress	1.367m	361.691us	50	50	100.00
V2	key_length	aes_smoke	1.617m	154.566us	50	50	100.00
		aes_config_error	1.350m	2.966ms	50	50	100.00
		aes_stress	1.367m	361.691us	50	50	100.00
V2	back2back	aes_stress	1.367m	361.691us	50	50	100.00
		aes_b2b	1.983m	830.536us	50	50	100.00
V2	backpressure	aes_stress	1.367m	361.691us	50	50	100.00
V2	multi_message	aes_smoke	1.617m	154.566us	50	50	100.00
		aes_config_error	1.350m	2.966ms	50	50	100.00
		aes_stress	1.367m	361.691us	50	50	100.00
		aes_alert_reset	2.017m	5.876ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.100m	68.492us	50	50	100.00
		aes_config_error	1.350m	2.966ms	50	50	100.00
		aes_alert_reset	2.017m	5.876ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.217m	125.606us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	311.758us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.017m	5.876ms	50	50	100.00
V2	stress	aes_stress	1.367m	361.691us	50	50	100.00
V2	sideload	aes_stress	1.367m	361.691us	50	50	100.00
		aes_sideload	2.133m	110.009us	50	50	100.00
V2	deinitialization	aes_deinit	2.133m	76.674us	50	50	100.00
V2	stress_all	aes_stress_all	1.583m	7.035ms	10	10	100.00
V2	alert_test	aes_alert_test	1.433m	76.465us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	58.000s	90.502us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	58.000s	90.502us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	56.000s	78.527us	5	5	100.00
		aes_csr_rw	55.000s	64.248us	20	20	100.00
		aes_csr_aliasing	57.000s	372.364us	5	5	100.00
		aes_same_csr_outstanding	54.000s	94.132us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	56.000s	78.527us	5	5	100.00
		aes_csr_rw	55.000s	64.248us	20	20	100.00
		aes_csr_aliasing	57.000s	372.364us	5	5	100.00
		aes_same_csr_outstanding	54.000s	94.132us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.000m	8.072ms	50	50	100.00
V2S	fault_inject	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	56.000s	59.004us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	56.000s	59.004us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	56.000s	59.004us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	56.000s	59.004us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	56.000s	98.793us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.492ms	5	5	100.00
		aes_tl_intg_err	58.000s	292.728us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	58.000s	292.728us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.017m	5.876ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	56.000s	59.004us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.617m	154.566us	50	50	100.00
		aes_stress	1.367m	361.691us	50	50	100.00
		aes_alert_reset	2.017m	5.876ms	50	50	100.00
		aes_core_fi	2.100m	99.386us	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	56.000s	59.004us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.083m	148.703us	50	50	100.00
		aes_stress	1.367m	361.691us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.367m	361.691us	50	50	100.00
		aes_sideload	2.133m	110.009us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.083m	148.703us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.083m	148.703us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.083m	148.703us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.083m	148.703us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.083m	148.703us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.367m	361.691us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.367m	361.691us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.783m	659.341us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
		aes_ctr_fi	56.000s	160.168us	46	50	92.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.783m	659.341us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	58.650us	315	350	90.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.783m	659.341us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_ctr_fi	56.000s	160.168us	46	50	92.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
		aes_ctr_fi	56.000s	160.168us	46	50	92.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.017m	5.876ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
		aes_ctr_fi	56.000s	160.168us	46	50	92.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
		aes_ctr_fi	56.000s	160.168us	46	50	92.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_ctr_fi	56.000s	160.168us	46	50	92.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.783m	659.341us	49	50	98.00
		aes_control_fi	1.000m	58.041us	256	300	85.33
		aes_cipher_fi	1.017m	58.650us	315	350	90.00
V2S		TOTAL			897	985	91.07
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	40.000s	783.532us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1504	1602	93.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.55	96.32	99.45	95.82	97.72	100.00	98.96	96.81

Failure Buckets

Job timed out after * minutes has 77 failures:
- Test aes_control_fi has 43 failures.
  - 4.aes_control_fi.76031548944401251454888986571364304654104722250328372243568848489504805097867
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 6.aes_control_fi.24752322905880061127832085102291957155192231969023851905338706231004616075070
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 41 more failures.
- Test aes_cipher_fi has 30 failures.
  - 29.aes_cipher_fi.70955345756915188225686732310798186872132477866882695958703636096568895487688
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 40.aes_cipher_fi.90994083524547586691131546989144143523174676854998454740376183834659168640763
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 28 more failures.
- Test aes_ctr_fi has 4 failures.
  - 36.aes_ctr_fi.53507980364943030816132809574477014192642724707103664204337801423746506008333
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/36.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 39.aes_ctr_fi.19774536199719784631579327683218860304469499986166163686970693978631636347522
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/39.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 17.aes_cipher_fi.44447567011051970528167767279635153026378005354887730508930747944976551433170
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006160108 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006160108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.aes_cipher_fi.84457388887438253462563694302897921599022429230260406444512967322923305685232
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/56.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013299370 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013299370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test aes_stress_all_with_rand_reset has 4 failures.
  - 0.aes_stress_all_with_rand_reset.59893744727139046418541326421022657289485164923751113980496815667265613124091
    Line 214, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 509888243 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 509888243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.aes_stress_all_with_rand_reset.53913764441668177055650572874457120347131461706138354144447347902164479025740
    Line 267, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1804942094 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1804942094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.2299348175041771739627527209350443791358318493852369855902675656897444606228
Line 161, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 136217701 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 136217701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.45524491296099073891872855705110490623279498728530041965529297522913617227771
Line 624, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1193450918 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1193450918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 25.aes_core_fi.4223388488194406717858004615985576758130420808458670568336589918755519224494
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10044162827 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044162827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.35350566178529613996324755049828108208545499710046156909008948094758943803685
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007321150 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007321150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 0.aes_fi.19341957890734984642205813384745737047733194452412778748258318190042003613964
    Line 15375, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/0.aes_fi/latest/run.log
```
  UVM_FATAL @  89199603 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  89199603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.101058853737638354641861568666099680308654899178668100874652042332557642777995
    Line 173, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 149238828 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 149238828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_control_fi has 1 failures.
  - 5.aes_control_fi.43086232274153273919853421905087411994837171836664909885899020963119014715488
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011838986 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011838986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.62058754951131539764076163868350510720533923452357457086489674383406627345981
    Line 613, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 659389213 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 659389213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```