AES/MASKED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	136.005us	1	1	100.00
V1	smoke	aes_smoke	1.417m	99.401us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	72.046us	5	5	100.00
V1	csr_rw	aes_csr_rw	17.000s	59.496us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.830ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	280.247us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	17.000s	73.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	17.000s	59.496us	20	20	100.00
		aes_csr_aliasing	6.000s	280.247us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.417m	99.401us	50	50	100.00
		aes_config_error	1.667m	102.027us	50	50	100.00
		aes_stress	1.367m	2.642ms	50	50	100.00
V2	key_length	aes_smoke	1.417m	99.401us	50	50	100.00
		aes_config_error	1.667m	102.027us	50	50	100.00
		aes_stress	1.367m	2.642ms	50	50	100.00
V2	back2back	aes_stress	1.367m	2.642ms	50	50	100.00
		aes_b2b	1.550m	726.461us	50	50	100.00
V2	backpressure	aes_stress	1.367m	2.642ms	50	50	100.00
V2	multi_message	aes_smoke	1.417m	99.401us	50	50	100.00
		aes_config_error	1.667m	102.027us	50	50	100.00
		aes_stress	1.367m	2.642ms	50	50	100.00
		aes_alert_reset	1.733m	324.023us	49	50	98.00
V2	failure_test	aes_man_cfg_err	1.633m	81.692us	50	50	100.00
		aes_config_error	1.667m	102.027us	50	50	100.00
		aes_alert_reset	1.733m	324.023us	49	50	98.00
V2	trigger_clear_test	aes_clear	1.400m	736.989us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	18.000s	1.038ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.733m	324.023us	49	50	98.00
V2	stress	aes_stress	1.367m	2.642ms	50	50	100.00
V2	sideload	aes_stress	1.367m	2.642ms	50	50	100.00
		aes_sideload	1.500m	78.608us	50	50	100.00
V2	deinitialization	aes_deinit	1.650m	115.963us	50	50	100.00
V2	stress_all	aes_stress_all	1.450m	2.514ms	10	10	100.00
V2	alert_test	aes_alert_test	1.517m	57.440us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	19.000s	532.239us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	19.000s	532.239us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	72.046us	5	5	100.00
		aes_csr_rw	17.000s	59.496us	20	20	100.00
		aes_csr_aliasing	6.000s	280.247us	5	5	100.00
		aes_same_csr_outstanding	17.000s	137.350us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	72.046us	5	5	100.00
		aes_csr_rw	17.000s	59.496us	20	20	100.00
		aes_csr_aliasing	6.000s	280.247us	5	5	100.00
		aes_same_csr_outstanding	17.000s	137.350us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.733m	106.417us	50	50	100.00
V2S	fault_inject	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	17.000s	55.122us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	17.000s	55.122us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	17.000s	55.122us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	17.000s	55.122us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	17.000s	86.758us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	547.187us	5	5	100.00
		aes_tl_intg_err	18.000s	119.068us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	18.000s	119.068us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.733m	324.023us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	17.000s	55.122us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.417m	99.401us	50	50	100.00
		aes_stress	1.367m	2.642ms	50	50	100.00
		aes_alert_reset	1.733m	324.023us	49	50	98.00
		aes_core_fi	1.600m	10.018ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	17.000s	55.122us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.633m	101.461us	50	50	100.00
		aes_stress	1.367m	2.642ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.367m	2.642ms	50	50	100.00
		aes_sideload	1.500m	78.608us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.633m	101.461us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.633m	101.461us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.633m	101.461us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.633m	101.461us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.633m	101.461us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.367m	2.642ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.367m	2.642ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.500m	124.862us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
		aes_ctr_fi	1.000m	76.793us	47	50	94.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.500m	124.862us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	140.888us	306	350	87.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.500m	124.862us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_ctr_fi	1.000m	76.793us	47	50	94.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
		aes_ctr_fi	1.000m	76.793us	47	50	94.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.733m	324.023us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
		aes_ctr_fi	1.000m	76.793us	47	50	94.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
		aes_ctr_fi	1.000m	76.793us	47	50	94.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_ctr_fi	1.000m	76.793us	47	50	94.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.500m	124.862us	50	50	100.00
		aes_control_fi	1.000m	48.858us	241	300	80.33
		aes_cipher_fi	59.000s	140.888us	306	350	87.43
V2S		TOTAL			877	985	89.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	52.000s	5.559ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1483	1602	92.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.33	98.53	96.25	99.42	95.72	97.64	97.78	98.96	97.01

Failure Buckets

Job timed out after * minutes has 97 failures:
- Test aes_cipher_fi has 38 failures.
  - 4.aes_cipher_fi.89676929814456633928312891712122275298980201821105710373122516501195912955873
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_cipher_fi.108993484918677269104317642258161124068961378977105648089792080451245315835813
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 36 more failures.
- Test aes_control_fi has 56 failures.
  - 14.aes_control_fi.14215695471106372856420074597192285660167455930560737671846360453934619671231
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 20.aes_control_fi.19496145983101215631802682588826295554951136506503422601092387431497614899172
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 54 more failures.
- Test aes_ctr_fi has 3 failures.
  - 14.aes_ctr_fi.39363283907830094641678695723696635547555225982673474971857791907906833412564
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/14.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_ctr_fi.13677250595215996582384818338090405099144810563179643503820145149367603170917
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/25.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.52076671725560051176196039970444766719438076356727572798843691190534187943909
Line 637, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 564572760 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 564572760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.111301333913542797539539858219793702267578734924148145796647903283128251205894
Line 398, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 505109981 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 505109981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 42.aes_cipher_fi.81296725788493917352731711687359910075397928803430654998879381868505864791614
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010642928 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010642928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.aes_cipher_fi.57080979024354382512873600887925086548759500248537656397414945989473514049614
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10031709790 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031709790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 39.aes_control_fi.95879737991844143786237762773315853018666986038092146212876430708057104404878
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10094372642 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10094372642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 74.aes_control_fi.32254834268218909957222896378352063608844937838879043411997045545191195709582
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10030793747 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030793747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.60406756296593180896581184849049649884935298029887296516273135858771006382083
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 228271038 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 228271038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.18840689553838046854997867577214793168877526193987415227220305744735249999932
    Line 185, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 232118300 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 232118300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 17.aes_core_fi.104206611416690649568660311129478433812447646299329413537807985535575980837032
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012533379 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012533379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_core_fi.87983592671152463065865632789225345676845995330799579414034252089657259492517
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017782496 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017782496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.45751157742261738844863120931180484959778432850061608777388898835738785613009
    Line 247, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 201499075 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 201499075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.52176809298994810153161236045347844855936178510292252059144829972611049583271
    Line 363, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2289917349 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2289917349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 45.aes_alert_reset.74638701792237922668489190357586455015679611778910987297606522358786457677959
    Line 2103, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/45.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 59873326 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 59857941 PS)
  UVM_ERROR @  59873326 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  59873326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```