AES/UNMASKED Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	114.888us	1	1	100.00
V1	smoke	aes_smoke	8.000s	88.872us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	92.411us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	72.310us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	4.152ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	499.514us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	220.418us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	72.310us	20	20	100.00
		aes_csr_aliasing	6.000s	499.514us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	88.872us	50	50	100.00
		aes_config_error	5.000s	111.373us	50	50	100.00
		aes_stress	10.000s	85.506us	50	50	100.00
V2	key_length	aes_smoke	8.000s	88.872us	50	50	100.00
		aes_config_error	5.000s	111.373us	50	50	100.00
		aes_stress	10.000s	85.506us	50	50	100.00
V2	back2back	aes_stress	10.000s	85.506us	50	50	100.00
		aes_b2b	10.000s	153.070us	50	50	100.00
V2	backpressure	aes_stress	10.000s	85.506us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	88.872us	50	50	100.00
		aes_config_error	5.000s	111.373us	50	50	100.00
		aes_stress	10.000s	85.506us	50	50	100.00
		aes_alert_reset	5.000s	205.087us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	115.789us	50	50	100.00
		aes_config_error	5.000s	111.373us	50	50	100.00
		aes_alert_reset	5.000s	205.087us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	270.685us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	879.062us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	205.087us	50	50	100.00
V2	stress	aes_stress	10.000s	85.506us	50	50	100.00
V2	sideload	aes_stress	10.000s	85.506us	50	50	100.00
		aes_sideload	8.000s	120.879us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	389.378us	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	423.351us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	106.117us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	191.057us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	191.057us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	92.411us	5	5	100.00
		aes_csr_rw	8.000s	72.310us	20	20	100.00
		aes_csr_aliasing	6.000s	499.514us	5	5	100.00
		aes_same_csr_outstanding	5.000s	166.801us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	92.411us	5	5	100.00
		aes_csr_rw	8.000s	72.310us	20	20	100.00
		aes_csr_aliasing	6.000s	499.514us	5	5	100.00
		aes_same_csr_outstanding	5.000s	166.801us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	180.246us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	359.767us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	359.767us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	359.767us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	359.767us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	97.897us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.593ms	5	5	100.00
		aes_tl_intg_err	10.000s	285.315us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	285.315us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	205.087us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	359.767us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	88.872us	50	50	100.00
		aes_stress	10.000s	85.506us	50	50	100.00
		aes_alert_reset	5.000s	205.087us	50	50	100.00
		aes_core_fi	35.000s	10.016ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	359.767us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	67.460us	50	50	100.00
		aes_stress	10.000s	85.506us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	85.506us	50	50	100.00
		aes_sideload	8.000s	120.879us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	67.460us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	67.460us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	67.460us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	67.460us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	67.460us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	85.506us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	85.506us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	90.840us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
		aes_ctr_fi	13.000s	108.007us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	90.840us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	41.469ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	90.840us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_ctr_fi	13.000s	108.007us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
		aes_ctr_fi	13.000s	108.007us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	205.087us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
		aes_ctr_fi	13.000s	108.007us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
		aes_ctr_fi	13.000s	108.007us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_ctr_fi	13.000s	108.007us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	90.840us	50	50	100.00
		aes_control_fi	46.000s	32.846ms	280	300	93.33
		aes_cipher_fi	49.000s	41.469ms	324	350	92.57
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	35.000s	1.531ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1545	1602	96.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.33	93.96	98.81	93.65	97.64	91.11	98.85	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_cipher_fi has 18 failures.
  - 2.aes_cipher_fi.15718259866807429447613845240833708373826424654027531960925557246198259200539
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:09965e77-584d-44ef-b748-bb49332b12e3
```
  - 11.aes_cipher_fi.101045534902612855517071523402266409127154807268607456706427118210096609233694
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e4b6c403-9a1f-4117-b036-a66b30f8634a
```
  - ... and 16 more failures.
- Test aes_control_fi has 13 failures.
  - 4.aes_control_fi.37552763147865820798914930326447426739138029668181043415326924717868942963334
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:504eb8a2-aa4c-43bb-9c67-f3865bed2d9f
```
  - 39.aes_control_fi.67981382994284576035472515912010677653675221149286182403047781845331136505241
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  Job ID: smart:76ab169a-cfbb-4a17-a4f0-fd1cde783614
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 55.aes_cipher_fi.102315206366462844210328349261379516382348439633418336435883784646170273965848
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002287514 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002287514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 166.aes_cipher_fi.31226987210828637322275979591740472355007718377634180688630013987716361817704
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/166.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013297496 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013297496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 21.aes_control_fi.83232006222636487650962949333922585729800598658527878818776474524929966979320
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009514407 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009514407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.aes_control_fi.106026251087424837714814325656547794052490952775373689125464813505375844933208
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002411582 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002411582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.88050113466035114334966960385552282168899865768763889091942456341312843459257
Line 1523, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1530975764 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1530975764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.52342372382728323483230838301472642249462281710694707647513747917978165649578
Line 1436, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1686531513 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1686531513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.34618856401279071206704107790874111786018238540410553037168388593733515134970
Line 1257, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1223604379 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1223604379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.78765592007073465413761842279406301060817529284028732378456324172279041109580
Line 1016, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2512947773 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2512947773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd aes_reg_block.status (addr=*) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.30466636170796301882068712890996376619170925338003131599057090973488612123312
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2015700900 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd aes_reg_block.status (addr=0xf8500c84)
  UVM_INFO @ 2015700900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.83006386856386284948441244750462425358299821718613041509328692272590067448315
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015954004 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015954004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```