AES/UNMASKED Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	61.677us	1	1	100.00
V1	smoke	aes_smoke	6.000s	202.797us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.153us	5	5	100.00
V1	csr_rw	aes_csr_rw	33.000s	10.025ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	229.037us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	703.374us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	54.625us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	33.000s	10.025ms	19	20	95.00
		aes_csr_aliasing	9.000s	703.374us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	6.000s	202.797us	50	50	100.00
		aes_config_error	8.000s	63.603us	50	50	100.00
		aes_stress	9.000s	259.980us	50	50	100.00
V2	key_length	aes_smoke	6.000s	202.797us	50	50	100.00
		aes_config_error	8.000s	63.603us	50	50	100.00
		aes_stress	9.000s	259.980us	50	50	100.00
V2	back2back	aes_stress	9.000s	259.980us	50	50	100.00
		aes_b2b	10.000s	144.035us	50	50	100.00
V2	backpressure	aes_stress	9.000s	259.980us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	202.797us	50	50	100.00
		aes_config_error	8.000s	63.603us	50	50	100.00
		aes_stress	9.000s	259.980us	50	50	100.00
		aes_alert_reset	5.000s	309.270us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	70.934us	50	50	100.00
		aes_config_error	8.000s	63.603us	50	50	100.00
		aes_alert_reset	5.000s	309.270us	49	50	98.00
V2	trigger_clear_test	aes_clear	7.000s	1.131ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	976.618us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	309.270us	49	50	98.00
V2	stress	aes_stress	9.000s	259.980us	50	50	100.00
V2	sideload	aes_stress	9.000s	259.980us	50	50	100.00
		aes_sideload	5.000s	58.708us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	242.966us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	555.883us	9	10	90.00
V2	alert_test	aes_alert_test	17.000s	89.554us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	204.192us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	204.192us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.153us	5	5	100.00
		aes_csr_rw	33.000s	10.025ms	19	20	95.00
		aes_csr_aliasing	9.000s	703.374us	5	5	100.00
		aes_same_csr_outstanding	4.000s	132.885us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.153us	5	5	100.00
		aes_csr_rw	33.000s	10.025ms	19	20	95.00
		aes_csr_aliasing	9.000s	703.374us	5	5	100.00
		aes_same_csr_outstanding	4.000s	132.885us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	9.000s	329.101us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	275.901us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	275.901us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	275.901us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	275.901us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	144.101us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	600.159us	5	5	100.00
		aes_tl_intg_err	5.000s	550.111us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	550.111us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	309.270us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	275.901us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	202.797us	50	50	100.00
		aes_stress	9.000s	259.980us	50	50	100.00
		aes_alert_reset	5.000s	309.270us	49	50	98.00
		aes_core_fi	2.833m	10.027ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	275.901us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	88.212us	50	50	100.00
		aes_stress	9.000s	259.980us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	259.980us	50	50	100.00
		aes_sideload	5.000s	58.708us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	88.212us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	88.212us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	88.212us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	88.212us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	88.212us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	259.980us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	259.980us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	76.051us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
		aes_ctr_fi	13.000s	100.409us	48	50	96.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	76.051us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	53.000s	65.640ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	76.051us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_ctr_fi	13.000s	100.409us	48	50	96.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
		aes_ctr_fi	13.000s	100.409us	48	50	96.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	309.270us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
		aes_ctr_fi	13.000s	100.409us	48	50	96.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
		aes_ctr_fi	13.000s	100.409us	48	50	96.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_ctr_fi	13.000s	100.409us	48	50	96.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	76.051us	49	50	98.00
		aes_control_fi	52.000s	40.416ms	275	300	91.67
		aes_cipher_fi	53.000s	65.640ms	333	350	95.14
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.950m	27.861ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	11	84.62
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.50	94.35	98.79	93.74	97.72	91.85	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_ctr_fi has 2 failures.
  - 13.aes_ctr_fi.91159852489587793659465755893672317590123992475730084104947212226434453637873
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job ID: smart:3ebfd0e4-f817-4aff-b868-e7173b0fd2fc
```
  - 33.aes_ctr_fi.4460364296883799855447403760694196508210208296973068232033248617554136451713
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_ctr_fi/latest/run.log
```
  Job ID: smart:0d0369b0-f0da-44a6-a7dc-5c8e4c3e4c1b
```
- Test aes_cipher_fi has 9 failures.
  - 18.aes_cipher_fi.58997079287320451288674950531486148742241219974994924031144136476179474696944
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:564aef8b-f811-42e6-aeae-1e592ef70a36
```
  - 49.aes_cipher_fi.109981828557314325225505431195193411466491828600868485195460687017534029506278
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3ba9d4cd-684c-46dc-86cc-4a137b07acea
```
  - ... and 7 more failures.
- Test aes_control_fi has 13 failures.
  - 45.aes_control_fi.51294484724520534362657623443540421078930001722377018231155918161173130509832
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:cfc6570d-262a-4960-a163-d66126451485
```
  - 57.aes_control_fi.12938038371793617984252207367482686958389666095974572067473242418395879172030
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  Job ID: smart:064b635a-6c77-4e91-86ea-1d7f713b08ea
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 7.aes_control_fi.17282759870985156251349659906249439889835986631821517015971008639245315424698
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008874618 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008874618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_control_fi.80064601447144031532952356327625982500970721221097266324938909257962819346474
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006249885 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006249885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 17.aes_cipher_fi.53607744656093364288879926960349356272530610791179809307957410461227614801544
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004716095 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004716095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.aes_cipher_fi.101021293836459961332976673269606937849218325823555863451230149241995005381406
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005817854 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005817854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

3.aes_stress_all_with_rand_reset.55101116231061935317857610358123593614580567488766543846568599943669838341301
Line 1811, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5954811428 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5954811428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.15637513555876290293949974226266737320738134760963447411936087999321032755423
Line 1760, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2932506849 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2932506849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 23.aes_core_fi.107558387117697094066720341796056266371515340321374440087222099317440484713251
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025034228 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025034228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_core_fi.91029893241568407292679249486898908848773904262173301497759575485171686299710
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017993286 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017993286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.43258165023976748062322581365415694210508161451728731073078335119699995719604
Line 749, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 425777924 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 425777924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.32204944669697480680877839230662271498025098856923721993444258180311785982713
Line 445, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9178153939 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9178153939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.23869061007693222759107684914378754467398057779991895148852608392798024686090
    Line 338, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120027040 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 120027040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 7.aes_stress_all.102771934755242874406632557910979621184487353969210697712922260131820408387693
    Line 59433, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 2841414700 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 2841374700 PS)
  UVM_ERROR @ 2841414700 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 2841414700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 13.aes_csr_rw.50014934423952537749067070733613584254692821764437319733357280590050166663623
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10024676495 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x870d9784) == 0x0
  UVM_INFO @ 10024676495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 18.aes_alert_reset.93174383239495796285979873983439020994000723147969784192035371898533923583218
    Line 4404, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_alert_reset/latest/run.log
```
  UVM_ERROR @  74029998 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  74029998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 20.aes_fi.86157459836944782724654987596542009819147191870951556832916237785440323092415
    Line 7958, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_fi/latest/run.log
```
  UVM_FATAL @  22809153 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  22809153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 53.aes_core_fi.111446940374990945492807415992401277976939571150859222694991884594441102657220
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10027318471 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x3a0a8184) == 0x0
  UVM_INFO @ 10027318471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```