AES/UNMASKED Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	337.260us	1	1	100.00
V1	smoke	aes_smoke	13.000s	55.327us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	94.568us	5	5	100.00
V1	csr_rw	aes_csr_rw	10.000s	84.575us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	507.246us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	161.638us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	64.847us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	10.000s	84.575us	20	20	100.00
		aes_csr_aliasing	5.000s	161.638us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	55.327us	50	50	100.00
		aes_config_error	14.000s	55.287us	50	50	100.00
		aes_stress	15.000s	85.333us	50	50	100.00
V2	key_length	aes_smoke	13.000s	55.327us	50	50	100.00
		aes_config_error	14.000s	55.287us	50	50	100.00
		aes_stress	15.000s	85.333us	50	50	100.00
V2	back2back	aes_stress	15.000s	85.333us	50	50	100.00
		aes_b2b	16.000s	174.508us	50	50	100.00
V2	backpressure	aes_stress	15.000s	85.333us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	55.327us	50	50	100.00
		aes_config_error	14.000s	55.287us	50	50	100.00
		aes_stress	15.000s	85.333us	50	50	100.00
		aes_alert_reset	18.000s	118.155us	49	50	98.00
V2	failure_test	aes_man_cfg_err	15.000s	59.129us	50	50	100.00
		aes_config_error	14.000s	55.287us	50	50	100.00
		aes_alert_reset	18.000s	118.155us	49	50	98.00
V2	trigger_clear_test	aes_clear	10.000s	412.295us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	481.946us	1	1	100.00
V2	reset_recovery	aes_alert_reset	18.000s	118.155us	49	50	98.00
V2	stress	aes_stress	15.000s	85.333us	50	50	100.00
V2	sideload	aes_stress	15.000s	85.333us	50	50	100.00
		aes_sideload	10.000s	80.269us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	79.439us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	4.684ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	80.838us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	199.268us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	199.268us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	94.568us	5	5	100.00
		aes_csr_rw	10.000s	84.575us	20	20	100.00
		aes_csr_aliasing	5.000s	161.638us	5	5	100.00
		aes_same_csr_outstanding	5.000s	66.914us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	94.568us	5	5	100.00
		aes_csr_rw	10.000s	84.575us	20	20	100.00
		aes_csr_aliasing	5.000s	161.638us	5	5	100.00
		aes_same_csr_outstanding	5.000s	66.914us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	38.000s	803.848us	50	50	100.00
V2S	fault_inject	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	85.563us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	85.563us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	85.563us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	85.563us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	1.110ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	762.030us	5	5	100.00
		aes_tl_intg_err	10.000s	358.717us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	358.717us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	18.000s	118.155us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	85.563us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	55.327us	50	50	100.00
		aes_stress	15.000s	85.333us	50	50	100.00
		aes_alert_reset	18.000s	118.155us	49	50	98.00
		aes_core_fi	1.800m	10.039ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	85.563us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	67.687us	50	50	100.00
		aes_stress	15.000s	85.333us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	85.333us	50	50	100.00
		aes_sideload	10.000s	80.269us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	67.687us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	67.687us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	67.687us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	67.687us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	67.687us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	85.333us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	85.333us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	100.134us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
		aes_ctr_fi	9.000s	92.702us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	100.134us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	35.032ms	321	350	91.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	100.134us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_ctr_fi	9.000s	92.702us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
		aes_ctr_fi	9.000s	92.702us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	18.000s	118.155us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
		aes_ctr_fi	9.000s	92.702us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
		aes_ctr_fi	9.000s	92.702us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_ctr_fi	9.000s	92.702us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	100.134us	50	50	100.00
		aes_control_fi	52.000s	31.533ms	275	300	91.67
		aes_cipher_fi	48.000s	35.032ms	321	350	91.71
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	48.000s	6.867ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1531	1602	95.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.50	94.35	98.77	93.60	97.64	91.11	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_cipher_fi has 15 failures.
  - 4.aes_cipher_fi.67826577627275911482959629998168780752893697672124033874925644896611810211016
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8f6843f7-eff8-4c91-87b8-f512a1bd6c98
```
  - 67.aes_cipher_fi.101235602717189698546448116037485969471602828483069840419304887094449557469370
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_cipher_fi/latest/run.log
```
  Job ID: smart:312bd8b1-1ac8-427b-8b03-3489d6449143
```
  - ... and 13 more failures.
- Test aes_control_fi has 16 failures.
  - 13.aes_control_fi.60276009492448457372277117396493895631920247230218913764643342467487908243066
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:ab26126f-b7a7-4ca5-854a-7edf079fae7d
```
  - 45.aes_control_fi.101825292065135528283851060261292302733033253629511501437108199178778043436575
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:90b3e14f-dc57-4158-a7dd-76d78731bd34
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 5.aes_cipher_fi.96051979403900313917955788059759701635824608384184791340309873009676611062540
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10031408095 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031408095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 107.aes_cipher_fi.81029581189308269301876225374901433502947369112883234335681977522139563690562
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/107.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003045539 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003045539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 52.aes_control_fi.107702194000256849137126156975557127468038591630664288929818014422296092384691
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002561408 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002561408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_control_fi.16725977536413859600826066288836152324185707106069173380619856913523981663167
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002396711 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002396711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.80243355509075611841389139844952232623980515401019775000815502329409737177765
Line 638, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 146742029 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 146742029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.55717790525311616014445887282744571727933003040728638934152989352129004181450
Line 1192, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2619396831 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2619396831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 20.aes_core_fi.114153016042553426310885013633940342565324748010035290718447213964043732763988
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007491858 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007491858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_core_fi.89778565743544398247187371903962423300094166465410885416406702472242351199633
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006467428 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006467428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.114705718684390815229634694940638621577256182258490733422846163135699407420944
Line 851, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 504446283 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 504446283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.106998943432245171500446157826450357094497517868438139664388679801978661561228
Line 1715, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 912579736 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 912579736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 34.aes_alert_reset.7746119204732434382980491346415946815680484693856342729137856037432809839767
    Line 3493, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 9627935 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9617834 PS)
  UVM_ERROR @   9627935 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   9627935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 40.aes_core_fi.26312271455510048693514571353151722768952194155263946092473808256300258070636
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039324022 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x3cee7f84) == 0x0
  UVM_INFO @ 10039324022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 62.aes_core_fi.55834896750586255932705599178110191670846910180095545613248164149946042378101
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021664852 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021664852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 110.aes_cipher_fi.90790379349671951885820865258700593912380021183508640674688456510986159352611
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/110.aes_cipher_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 7326968 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 7316968 PS)
  UVM_ERROR @   7326968 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   7326968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```