AES/UNMASKED Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	54.279us	1	1	100.00
V1	smoke	aes_smoke	9.000s	72.770us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	87.272us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	125.304us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.218ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	220.511us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	113.884us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	125.304us	20	20	100.00
		aes_csr_aliasing	5.000s	220.511us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	72.770us	50	50	100.00
		aes_config_error	14.000s	231.067us	50	50	100.00
		aes_stress	16.000s	129.526us	50	50	100.00
V2	key_length	aes_smoke	9.000s	72.770us	50	50	100.00
		aes_config_error	14.000s	231.067us	50	50	100.00
		aes_stress	16.000s	129.526us	50	50	100.00
V2	back2back	aes_stress	16.000s	129.526us	50	50	100.00
		aes_b2b	11.000s	84.719us	50	50	100.00
V2	backpressure	aes_stress	16.000s	129.526us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	72.770us	50	50	100.00
		aes_config_error	14.000s	231.067us	50	50	100.00
		aes_stress	16.000s	129.526us	50	50	100.00
		aes_alert_reset	11.000s	101.473us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	156.342us	50	50	100.00
		aes_config_error	14.000s	231.067us	50	50	100.00
		aes_alert_reset	11.000s	101.473us	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	743.178us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	466.259us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	101.473us	50	50	100.00
V2	stress	aes_stress	16.000s	129.526us	50	50	100.00
V2	sideload	aes_stress	16.000s	129.526us	50	50	100.00
		aes_sideload	14.000s	370.663us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	68.245us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	1.309ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	72.154us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	1.228ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	1.228ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	87.272us	5	5	100.00
		aes_csr_rw	4.000s	125.304us	20	20	100.00
		aes_csr_aliasing	5.000s	220.511us	5	5	100.00
		aes_same_csr_outstanding	4.000s	154.516us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	87.272us	5	5	100.00
		aes_csr_rw	4.000s	125.304us	20	20	100.00
		aes_csr_aliasing	5.000s	220.511us	5	5	100.00
		aes_same_csr_outstanding	4.000s	154.516us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	15.000s	764.264us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	172.347us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	172.347us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	172.347us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	172.347us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	213.857us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	806.912us	5	5	100.00
		aes_tl_intg_err	5.000s	522.995us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	522.995us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	101.473us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	172.347us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	72.770us	50	50	100.00
		aes_stress	16.000s	129.526us	50	50	100.00
		aes_alert_reset	11.000s	101.473us	50	50	100.00
		aes_core_fi	1.233m	10.064ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	172.347us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	77.495us	50	50	100.00
		aes_stress	16.000s	129.526us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	129.526us	50	50	100.00
		aes_sideload	14.000s	370.663us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	77.495us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	77.495us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	77.495us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	77.495us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	77.495us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	129.526us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	129.526us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	67.936us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
		aes_ctr_fi	8.000s	60.529us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	67.936us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.002ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	67.936us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_ctr_fi	8.000s	60.529us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
		aes_ctr_fi	8.000s	60.529us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	101.473us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
		aes_ctr_fi	8.000s	60.529us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
		aes_ctr_fi	8.000s	60.529us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_ctr_fi	8.000s	60.529us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	67.936us	50	50	100.00
		aes_control_fi	48.000s	31.546ms	285	300	95.00
		aes_cipher_fi	51.000s	10.002ms	328	350	93.71
V2S		TOTAL			945	985	95.94
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	9.450m	77.097ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.50	94.35	98.77	93.80	97.72	93.33	98.66	96.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_cipher_fi has 15 failures.
  - 7.aes_cipher_fi.107892499732885886260399561478838110358257548437529495917690126719526492953395
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bae9013b-9d1a-4c7c-a165-e0b2dc240b66
```
  - 18.aes_cipher_fi.52287817161397415895726108369918886994028948184327155122795406769786113678407
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2018284e-55db-4baf-9f15-ec3bee095ac8
```
  - ... and 13 more failures.
- Test aes_control_fi has 10 failures.
  - 42.aes_control_fi.104963263074172318788366039387499445843790480160958476485992622807005575347379
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job ID: smart:cfd5cda2-b459-40a5-81e2-c21e861e80e4
```
  - 91.aes_control_fi.68066339995309689065532390700291821823238875825690721677160048660493866620316
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/91.aes_control_fi/latest/run.log
```
  Job ID: smart:aa70bec0-4fe0-4a12-a8c0-f20380395964
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 28.aes_cipher_fi.11347915841764943613962317972120143159384538685433613400880876256336506839308
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008843984 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008843984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.aes_cipher_fi.40707493201043275961087403308072762212897519263256193979501910922217301323424
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002097977 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002097977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.96267332561747042232167696385682309934889440201032183583373176523736373313856
Line 774, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1324842687 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1324842687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.13996096609491417339567688801528798584901090151221311661736811468416784412972
Line 1383, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2699092155 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2699092155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 85.aes_control_fi.14911511650835206537341512726812599905162290400598017607858135913998133205835
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/85.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010349326 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010349326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 105.aes_control_fi.57820361121098229709070566692744721607029733959296047006552275753282155795616
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/105.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005974161 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005974161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.67281061256306199181592238039700746919859605972259026330377151026621314090401
Line 1879, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4510372755 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4510372755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.20977025922058375932762006509034161405247451024595553315702690732335687156059
Line 858, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2279664905 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2279664905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 4.aes_core_fi.109227851171883105462824613308191130023781669589536009301667493386243852202019
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011581909 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011581909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.38727188103978857048670516108551801449962074799937472930887752264503236433143
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10064179524 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x624f7d84) == 0x0
  UVM_INFO @ 10064179524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 41.aes_core_fi.71138491631862106294265304772568674269120635648829027538357569729716261125112
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006348788 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006348788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```