AES/UNMASKED Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	61.518us	1	1	100.00
V1	smoke	aes_smoke	14.000s	61.917us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.380us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	106.794us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.661ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	278.993us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	121.555us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	106.794us	20	20	100.00
		aes_csr_aliasing	5.000s	278.993us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	14.000s	61.917us	50	50	100.00
		aes_config_error	9.000s	108.577us	50	50	100.00
		aes_stress	13.000s	110.845us	50	50	100.00
V2	key_length	aes_smoke	14.000s	61.917us	50	50	100.00
		aes_config_error	9.000s	108.577us	50	50	100.00
		aes_stress	13.000s	110.845us	50	50	100.00
V2	back2back	aes_stress	13.000s	110.845us	50	50	100.00
		aes_b2b	20.000s	130.587us	50	50	100.00
V2	backpressure	aes_stress	13.000s	110.845us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	61.917us	50	50	100.00
		aes_config_error	9.000s	108.577us	50	50	100.00
		aes_stress	13.000s	110.845us	50	50	100.00
		aes_alert_reset	9.000s	121.615us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	72.107us	50	50	100.00
		aes_config_error	9.000s	108.577us	50	50	100.00
		aes_alert_reset	9.000s	121.615us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	160.883us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	829.773us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	121.615us	50	50	100.00
V2	stress	aes_stress	13.000s	110.845us	50	50	100.00
V2	sideload	aes_stress	13.000s	110.845us	50	50	100.00
		aes_sideload	15.000s	247.026us	50	50	100.00
V2	deinitialization	aes_deinit	19.000s	132.691us	50	50	100.00
V2	stress_all	aes_stress_all	23.000s	3.194ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	99.399us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	438.428us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	438.428us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.380us	5	5	100.00
		aes_csr_rw	4.000s	106.794us	20	20	100.00
		aes_csr_aliasing	5.000s	278.993us	5	5	100.00
		aes_same_csr_outstanding	15.000s	148.403us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.380us	5	5	100.00
		aes_csr_rw	4.000s	106.794us	20	20	100.00
		aes_csr_aliasing	5.000s	278.993us	5	5	100.00
		aes_same_csr_outstanding	15.000s	148.403us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	217.219us	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	73.076us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	73.076us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	73.076us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	73.076us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	134.558us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	869.914us	5	5	100.00
		aes_tl_intg_err	7.000s	640.690us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	640.690us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	121.615us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	73.076us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	61.917us	50	50	100.00
		aes_stress	13.000s	110.845us	50	50	100.00
		aes_alert_reset	9.000s	121.615us	50	50	100.00
		aes_core_fi	1.617m	10.036ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	73.076us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	60.118us	50	50	100.00
		aes_stress	13.000s	110.845us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	110.845us	50	50	100.00
		aes_sideload	15.000s	247.026us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	60.118us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	60.118us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	60.118us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	60.118us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	60.118us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	110.845us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	110.845us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	96.427us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
		aes_ctr_fi	13.000s	60.372us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	96.427us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	63.028ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	96.427us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_ctr_fi	13.000s	60.372us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
		aes_ctr_fi	13.000s	60.372us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	121.615us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
		aes_ctr_fi	13.000s	60.372us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
		aes_ctr_fi	13.000s	60.372us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_ctr_fi	13.000s	60.372us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	96.427us	50	50	100.00
		aes_control_fi	49.000s	16.111ms	279	300	93.00
		aes_cipher_fi	52.000s	63.028ms	337	350	96.29
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	28.000s	835.232us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1554	1602	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.46	94.26	98.81	93.63	97.72	93.33	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
- Test aes_control_fi has 16 failures.
  - 1.aes_control_fi.30520543833440389874139802320559339064608403413386926558686264623190691414267
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:42dddab8-ae29-4580-bea5-367aba5c05b5
```
  - 25.aes_control_fi.2707536329160783426228714110982101509514377106829333786426662811482024860087
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job ID: smart:4adfc730-f12e-4021-9356-4384e154a674
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 11 failures.
  - 26.aes_cipher_fi.42490222308888220932227497618466944272049926125385412138050578280282162375409
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ff6af406-410d-42aa-a717-4d08036647e5
```
  - 66.aes_cipher_fi.82099682523089301655707109581718041329909215776994330990348927825908143781796
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f1c68d40-01b6-4a4b-834d-fe423c060f9d
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 141.aes_control_fi.6700815203191175070547157088228940751400181241105554618167678131690246561989
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/141.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003123048 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003123048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 145.aes_control_fi.30514554701957128857867230593178808225377221787132206951444725791572926863227
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/145.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006834823 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006834823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.43708466310131608855145505294138416532674419543110097400309038238286795623170
Line 804, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1054707822 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1054707822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.45304529907915969462924424569671714835147358278861663202692260204253391921023
Line 925, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 219803569 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 219803569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.3190336824516716149907753544372116741866022137451729401463518007218635800610
Line 1047, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1326114566 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1326114566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.15480661681962921452048448081896815998891865406593104538744892377873735472445
Line 1745, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3746203105 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3746203105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_cipher_fi has 2 failures.
  - 6.aes_cipher_fi.109361667914127124730413248148137140528532797444804674777170219928181248445306
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012160442 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012160442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 147.aes_cipher_fi.109408155707607664069240224104368436891417244540811675910657653757857181046255
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/147.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012149786 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012149786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 8.aes_core_fi.18218381124333213283783011538486962339635764438607011520418004968737118861063
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008303796 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008303796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_core_fi.86156856527220349154011526472220683595524964272786531709068285528110655298503
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008894550 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008894550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.aes_csr_mem_rw_with_rand_reset.14764529330227102351097344203803646228603671426209749774066811548996168622909
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 121555062 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 121555062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.110542161729973045542222039415527526022401631233037157912585039174443562953240
    Line 419, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1556538267 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1556538267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.19856844741345943155550657727401447292633902780604828265519353066775371806193
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  93846865 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  93846865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 15.aes_core_fi.62844039794505260187421605533522296745005526029385566094452813449444950062383
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036316703 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xa5997884) == 0x0
  UVM_INFO @ 10036316703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```