AES/UNMASKED Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	85.044us	1	1	100.00
V1	smoke	aes_smoke	8.000s	135.748us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	56.163us	5	5	100.00
V1	csr_rw	aes_csr_rw	25.000s	10.041ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	2.631ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	220.342us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	61.925us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	25.000s	10.041ms	19	20	95.00
		aes_csr_aliasing	5.000s	220.342us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	8.000s	135.748us	50	50	100.00
		aes_config_error	13.000s	94.037us	50	50	100.00
		aes_stress	9.000s	341.259us	50	50	100.00
V2	key_length	aes_smoke	8.000s	135.748us	50	50	100.00
		aes_config_error	13.000s	94.037us	50	50	100.00
		aes_stress	9.000s	341.259us	50	50	100.00
V2	back2back	aes_stress	9.000s	341.259us	50	50	100.00
		aes_b2b	16.000s	156.268us	50	50	100.00
V2	backpressure	aes_stress	9.000s	341.259us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	135.748us	50	50	100.00
		aes_config_error	13.000s	94.037us	50	50	100.00
		aes_stress	9.000s	341.259us	50	50	100.00
		aes_alert_reset	9.000s	65.094us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	58.298us	50	50	100.00
		aes_config_error	13.000s	94.037us	50	50	100.00
		aes_alert_reset	9.000s	65.094us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	76.989us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	208.970us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	65.094us	50	50	100.00
V2	stress	aes_stress	9.000s	341.259us	50	50	100.00
V2	sideload	aes_stress	9.000s	341.259us	50	50	100.00
		aes_sideload	9.000s	61.621us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	79.549us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	654.856us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	64.400us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	1.574ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	1.574ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	56.163us	5	5	100.00
		aes_csr_rw	25.000s	10.041ms	19	20	95.00
		aes_csr_aliasing	5.000s	220.342us	5	5	100.00
		aes_same_csr_outstanding	2.217m	10.023ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	56.163us	5	5	100.00
		aes_csr_rw	25.000s	10.041ms	19	20	95.00
		aes_csr_aliasing	5.000s	220.342us	5	5	100.00
		aes_same_csr_outstanding	2.217m	10.023ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	8.000s	133.485us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	57.382us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	57.382us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	57.382us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	57.382us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	275.088us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	824.465us	5	5	100.00
		aes_tl_intg_err	5.000s	179.812us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	179.812us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	65.094us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	57.382us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	135.748us	50	50	100.00
		aes_stress	9.000s	341.259us	50	50	100.00
		aes_alert_reset	9.000s	65.094us	50	50	100.00
		aes_core_fi	45.000s	10.008ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	57.382us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	57.507us	50	50	100.00
		aes_stress	9.000s	341.259us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	341.259us	50	50	100.00
		aes_sideload	9.000s	61.621us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	57.507us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	57.507us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	57.507us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	57.507us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	57.507us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	341.259us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	341.259us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	76.697us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
		aes_ctr_fi	8.000s	89.636us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	76.697us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	52.514ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	76.697us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_ctr_fi	8.000s	89.636us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
		aes_ctr_fi	8.000s	89.636us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	65.094us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
		aes_ctr_fi	8.000s	89.636us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
		aes_ctr_fi	8.000s	89.636us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_ctr_fi	8.000s	89.636us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	76.697us	50	50	100.00
		aes_control_fi	51.000s	63.017ms	280	300	93.33
		aes_cipher_fi	52.000s	52.514ms	326	350	93.14
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.433m	6.356ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.05	97.41	94.14	98.75	93.16	97.72	91.11	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_control_fi has 13 failures.
  - 3.aes_control_fi.52967465733168642082805441540208896559062560739710235129764908987788743613777
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:51e86882-9982-42c2-b3f6-4f129de65a79
```
  - 10.aes_control_fi.18910559396232139687895966463380804728076095132404641814693515944583460139039
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:0b38c1fb-0710-4e75-8e87-2d418de004b4
```
  - ... and 11 more failures.
- Test aes_ctr_fi has 1 failures.
  - 12.aes_ctr_fi.53992681659660533115852097704086709460551929567631742252572935643079824632923
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_ctr_fi/latest/run.log
```
  Job ID: smart:af75d9a3-5c1d-4c70-a99d-6c17d20542c9
```
- Test aes_cipher_fi has 11 failures.
  - 30.aes_cipher_fi.111797726875121567174670261998160240410632503438850918649802069215539738816602
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cb588d6c-e262-4b6a-a582-211a1cf8f89c
```
  - 57.aes_cipher_fi.83844386049755084024413117280940728742721125439167805251307449941633675287431
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  Job ID: smart:20bf0bc8-0f4b-420f-9c28-fb6d5b5715f2
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 2.aes_cipher_fi.108089356364400426452275676146946379657458771273732285713009061683103178320911
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013296377 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013296377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.aes_cipher_fi.1515492671887135020773046976147696809696111172473674086071974960732510014826
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002494285 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002494285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.7624681698005599306303666889060344394488968113613491495723761934361879331148
Line 1605, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1836873248 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1836873248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.24878372554166666980297511181870960736547054399749851449736155235375855752940
Line 1544, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1620982764 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1620982764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 63.aes_control_fi.103201232367777480366505555780440133060189161361431769647130620222175009596668
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010168686 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010168686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.aes_control_fi.68689895261443110136279304579289167073123789204919747649736694231102554728087
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008466518 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008466518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.76237146203931951418752766809692455790039700704516033549790024657209676464330
Line 951, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1544392927 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1544392927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.16877566052479488010508943801690955577774111005865620290718010431438511742707
Line 1354, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1616873881 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1616873881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 2 failures:
- Test aes_csr_rw has 1 failures.
  - 8.aes_csr_rw.53814362490170972678269571075886484378162754450681050696983358769009131097793
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10041121643 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xc6540184) == 0x0
  UVM_INFO @ 10041121643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_same_csr_outstanding has 1 failures.
  - 9.aes_same_csr_outstanding.60622750261985930968384144480049494450901633937975342739701605042555895532534
    Line 293, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10023063545 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x680d6784) == 0x0
  UVM_INFO @ 10023063545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 43.aes_core_fi.106583018670683427741895873029418344174349430163647337559298827960251461145425
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007708892 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007708892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_core_fi.73152893611382305041824565852246607503938780750861754811371762856151500565107
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002838621 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002838621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```