AES/UNMASKED Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	73.965us	1	1	100.00
V1	smoke	aes_smoke	13.000s	53.187us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.042us	5	5	100.00
V1	csr_rw	aes_csr_rw	18.000s	53.096us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	517.046us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	416.308us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	78.617us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	18.000s	53.096us	20	20	100.00
		aes_csr_aliasing	6.000s	416.308us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	13.000s	53.187us	50	50	100.00
		aes_config_error	14.000s	469.054us	50	50	100.00
		aes_stress	14.000s	63.649us	50	50	100.00
V2	key_length	aes_smoke	13.000s	53.187us	50	50	100.00
		aes_config_error	14.000s	469.054us	50	50	100.00
		aes_stress	14.000s	63.649us	50	50	100.00
V2	back2back	aes_stress	14.000s	63.649us	50	50	100.00
		aes_b2b	18.000s	305.514us	50	50	100.00
V2	backpressure	aes_stress	14.000s	63.649us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	53.187us	50	50	100.00
		aes_config_error	14.000s	469.054us	50	50	100.00
		aes_stress	14.000s	63.649us	50	50	100.00
		aes_alert_reset	19.000s	140.102us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	58.481us	50	50	100.00
		aes_config_error	14.000s	469.054us	50	50	100.00
		aes_alert_reset	19.000s	140.102us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	76.823us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	116.181us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	140.102us	50	50	100.00
V2	stress	aes_stress	14.000s	63.649us	50	50	100.00
V2	sideload	aes_stress	14.000s	63.649us	50	50	100.00
		aes_sideload	14.000s	321.006us	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	81.975us	50	50	100.00
V2	stress_all	aes_stress_all	39.000s	976.940us	10	10	100.00
V2	alert_test	aes_alert_test	10.000s	90.963us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	2.725ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	2.725ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.042us	5	5	100.00
		aes_csr_rw	18.000s	53.096us	20	20	100.00
		aes_csr_aliasing	6.000s	416.308us	5	5	100.00
		aes_same_csr_outstanding	33.000s	10.217ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.042us	5	5	100.00
		aes_csr_rw	18.000s	53.096us	20	20	100.00
		aes_csr_aliasing	6.000s	416.308us	5	5	100.00
		aes_same_csr_outstanding	33.000s	10.217ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	16.000s	96.010us	50	50	100.00
V2S	fault_inject	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	77.072us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	77.072us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	77.072us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	77.072us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	129.898us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	19.000s	277.936us	5	5	100.00
		aes_tl_intg_err	9.000s	288.535us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	288.535us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	140.102us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	77.072us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	53.187us	50	50	100.00
		aes_stress	14.000s	63.649us	50	50	100.00
		aes_alert_reset	19.000s	140.102us	50	50	100.00
		aes_core_fi	15.000s	10.010ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	77.072us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	78.479us	50	50	100.00
		aes_stress	14.000s	63.649us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	63.649us	50	50	100.00
		aes_sideload	14.000s	321.006us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	78.479us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	78.479us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	78.479us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	78.479us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	78.479us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	63.649us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	63.649us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	23.000s	59.924us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
		aes_ctr_fi	18.000s	82.030us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	23.000s	59.924us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	87.503ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	23.000s	59.924us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_ctr_fi	18.000s	82.030us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
		aes_ctr_fi	18.000s	82.030us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	140.102us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
		aes_ctr_fi	18.000s	82.030us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
		aes_ctr_fi	18.000s	82.030us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_ctr_fi	18.000s	82.030us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	23.000s	59.924us	50	50	100.00
		aes_control_fi	50.000s	82.900ms	282	300	94.00
		aes_cipher_fi	52.000s	87.503ms	324	350	92.57
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.883m	8.597ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.46	94.26	98.81	93.54	97.72	93.33	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_cipher_fi has 17 failures.
  - 5.aes_cipher_fi.103537635085854999982971604746656695975067066972059162575243640925745918587764
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b4922a0f-4b46-4748-9e73-462590f6237d
```
  - 9.aes_cipher_fi.20785396693229076302589583388621936460091119673295424481689776582722387688549
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9a617fc5-75d3-4a48-af66-eee97e68f12d
```
  - ... and 15 more failures.
- Test aes_control_fi has 11 failures.
  - 28.aes_control_fi.90333957860966950807310747913055674261566963091896632701413726694518841366022
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job ID: smart:6e6e3ff2-68d7-4bc2-95f7-1049e782f9b4
```
  - 51.aes_control_fi.100081021585077972111057432087953666387677263018988946518828931884768939831694
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:3ad21fe8-c173-4fd9-b511-45831e37a93e
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 0.aes_cipher_fi.48552765705011591425177874154035799736701696472039096998201489751246754760287
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004851692 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004851692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 92.aes_cipher_fi.2096397622530299872843337357337136495506952968686575239735001710836249883013
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/92.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003084873 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003084873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

1.aes_stress_all_with_rand_reset.74364530646862533701893395082826326272303098142956229589679099020469396677773
Line 1414, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4543981282 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4543981282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.104480207450763670440491449286260264322762231950181230748054653696716417474316
Line 521, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3535780494 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3535780494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 23.aes_control_fi.162824679407466036334603933438659571751223765825771393747581340190410510289
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10023530692 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023530692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_control_fi.61494212885463407563426706454413248865270300766832987042108996637751827779205
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002180067 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002180067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 19.aes_core_fi.16007067123605549736892963662270061308644968292954322536624639539512459468894
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014836296 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014836296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_core_fi.106838070643933880549154380280478374858091095854153069576807240780784995309576
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010187434 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010187434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.109890787962740531651727530176778173457050846666088138947850753975621633673896
    Line 911, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 753971998 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 753930331 PS)
  UVM_ERROR @ 753971998 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 753971998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 7.aes_same_csr_outstanding.89202612138812303845558472280706025626692354990650873299736233003514216498899
    Line 301, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10216843904 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xed5d2684) == 0x0
  UVM_INFO @ 10216843904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.aes_csr_mem_rw_with_rand_reset.5275848416212605706911826500272009690700122471782814411950106297941707119793
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 124318763 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 124318763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```