eb56ef55d0
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
V1 | csr_hw_reset | aes_csr_hw_reset | 3.000s | 113.770us | 5 | 5 | 100.00 |
V1 | csr_rw | aes_csr_rw | 18.000s | 52.740us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | aes_csr_bit_bash | 10.000s | 587.197us | 5 | 5 | 100.00 |
V1 | csr_aliasing | aes_csr_aliasing | 14.000s | 396.621us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 12.000s | 74.878us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 18.000s | 52.740us | 20 | 20 | 100.00 |
aes_csr_aliasing | 14.000s | 396.621us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 55 | 106 | 51.89 | |||
V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
aes_config_error | 0 | 50 | 0.00 | ||||
aes_stress | 0 | 50 | 0.00 | ||||
V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
aes_config_error | 0 | 50 | 0.00 | ||||
aes_stress | 0 | 50 | 0.00 | ||||
V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
aes_b2b | 0 | 50 | 0.00 | ||||
V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
aes_config_error | 0 | 50 | 0.00 | ||||
aes_stress | 0 | 50 | 0.00 | ||||
aes_alert_reset | 0 | 50 | 0.00 | ||||
V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
aes_config_error | 0 | 50 | 0.00 | ||||
aes_alert_reset | 0 | 50 | 0.00 | ||||
V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
aes_sideload | 0 | 50 | 0.00 | ||||
V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
V2 | tl_d_oob_addr_access | aes_tl_errors | 15.000s | 547.140us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | aes_tl_errors | 15.000s | 547.140us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | aes_csr_hw_reset | 3.000s | 113.770us | 5 | 5 | 100.00 |
aes_csr_rw | 18.000s | 52.740us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 14.000s | 396.621us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 1.767m | 10.065ms | 19 | 20 | 95.00 | ||
V2 | tl_d_partial_access | aes_csr_hw_reset | 3.000s | 113.770us | 5 | 5 | 100.00 |
aes_csr_rw | 18.000s | 52.740us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 14.000s | 396.621us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 1.767m | 10.065ms | 19 | 20 | 95.00 | ||
V2 | TOTAL | 39 | 501 | 7.78 | |||
V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
V2S | shadow_reg_update_error | aes_shadow_reg_errors | 12.000s | 86.234us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 12.000s | 86.234us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 12.000s | 86.234us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 12.000s | 86.234us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 8.000s | 114.477us | 20 | 20 | 100.00 |
V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
aes_tl_intg_err | 9.000s | 268.654us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | aes_tl_intg_err | 9.000s | 268.654us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 12.000s | 86.234us | 20 | 20 | 100.00 |
V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
aes_stress | 0 | 50 | 0.00 | ||||
aes_alert_reset | 0 | 50 | 0.00 | ||||
aes_core_fi | 0 | 70 | 0.00 | ||||
V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 12.000s | 86.234us | 20 | 20 | 100.00 |
V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
aes_stress | 0 | 50 | 0.00 | ||||
V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
aes_sideload | 0 | 50 | 0.00 | ||||
V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
aes_ctr_fi | 0 | 50 | 0.00 | ||||
V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_ctr_fi | 0 | 50 | 0.00 | ||||
V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
aes_ctr_fi | 0 | 50 | 0.00 | ||||
V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
aes_ctr_fi | 0 | 50 | 0.00 | ||||
V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
aes_ctr_fi | 0 | 50 | 0.00 | ||||
V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_ctr_fi | 0 | 50 | 0.00 | ||||
V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
aes_control_fi | 0 | 300 | 0.00 | ||||
aes_cipher_fi | 0 | 350 | 0.00 | ||||
V2S | TOTAL | 60 | 985 | 6.09 | |||
V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
V3 | TOTAL | 0 | 10 | 0.00 | |||
TOTAL | 154 | 1602 | 9.61 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 5 | 71.43 |
V2 | 13 | 13 | 1 | 7.69 |
V2S | 11 | 11 | 3 | 27.27 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
84.08 | 99.63 | 98.89 | 100.00 | 99.74 | 44.47 | -- | 98.03 | 43.43 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable.
has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.39952719603601915421078211319785715731036628272065858766697943978139998489146
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.33879190190334407516438466891759967888008346583533689006828511080521870764873
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.43043785991324238781461850763917895427775011466044154205225726756359060135174
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.45914558624724202190564361210826161699369821830752574627155964655283186521692
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.98905701812577743980150575581900934345293879918235810586313056768790377730344
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.56962740125088778840732249259606180447161997825044402675079191329789676142374
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.98486025048067617371225314045133215759011095398439187218529397566749456657009
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.69370276622256491614450511908018159121499371648765994685907808758601006201209
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed.
has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.97287420236068346112419516479563284567752030153165806904759913248577056034928
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.114192784213407351207623316180626328747579397649280048226229117720928350129465
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.81958095757428509262352744258619606824098055812304876374917378535713215064350
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.63302026147115779890192392124691076505419211688822416612251623036714097691675
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.12095608216892591532949458095878564891001219541694084855196644138671905016609
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.105504257114218957799503523439242126939577312642213797103385349040638366666233
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.9859931891854748199955899982192514276704165996630690624053188557469221451503
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.6770157107730499897654954635183854393288573835603870976225952522737674391090
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == *
has 1 failures:
19.aes_same_csr_outstanding.99963745771249266360827942751300264817973296501357267265367221971581407327162
Line 300, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_same_csr_outstanding/latest/run.log
UVM_FATAL @ 10064619773 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xef356884) == 0x0
UVM_INFO @ 10064619773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---