e9ae10fb42| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 4.000s | 53.672us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 4.000s | 65.238us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 10.000s | 599.712us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 4.000s | 82.618us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 4.000s | 1.183ms | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 4.000s | 65.238us | 20 | 20 | 100.00 |
| aes_csr_aliasing | 4.000s | 82.618us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 54 | 106 | 50.94 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 7.000s | 286.187us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 7.000s | 286.187us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 4.000s | 53.672us | 5 | 5 | 100.00 |
| aes_csr_rw | 4.000s | 65.238us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 4.000s | 82.618us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 5.000s | 451.530us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 4.000s | 53.672us | 5 | 5 | 100.00 |
| aes_csr_rw | 4.000s | 65.238us | 20 | 20 | 100.00 | ||
| aes_csr_aliasing | 4.000s | 82.618us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 5.000s | 451.530us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 501 | 7.98 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 4.000s | 117.578us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 4.000s | 117.578us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 4.000s | 117.578us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 4.000s | 117.578us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 5.000s | 771.924us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 7.000s | 1.942ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 7.000s | 1.942ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 4.000s | 117.578us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 4.000s | 117.578us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 154 | 1602 | 9.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 13 | 13 | 2 | 15.38 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 84.10 | 99.63 | 98.89 | 100.00 | 99.74 | 44.47 | -- | 98.03 | 43.64 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.34149249166874738656915939331935958073304050286877575337052379313515264037135
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.91194290049214328147386692027078074619393286075578103550681912687894397347891
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.32464176340665133029937382098839254879094261897101320861286547240875702787447
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.74973683550397426319125323824581686457059129530904450516498328205390518224145
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.60865388783189789623785354996395160420985639201518580516635020209389784745048
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.41826240747902884040375662998874536168694399271363993026019273980340847447452
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.81636386204133379583290709675702469258336785419001252998423954576515717165805
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.33132305111724094954535485998657205771191144477193629942373193156160057607084
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.7621236268084516276730500328868919049224976538747069577826229014009710834142
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.23481846426646708906136213133982980215985246195088511761727853318748966904906
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.40960057863850685234049303943177710147089602412939084578034828299123027743130
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.36369303251137224830018688169182796634580524356429410917732756567007078790429
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.14624967901999261186587148926419555108365073927619931258787120533711638855802
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.10428618283031843316637191084764450456272470922087514812668134682573798317074
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.83290355689617335112060037510825242731501689624678492657877060730609919397142
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.9701435436782118217733453952380251471477679187364021998850803930419336044132
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
11.aes_csr_mem_rw_with_rand_reset.26927818786040635961015197025647625678617838853628120081964079956344293073754
Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1183134588 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1183134588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---