AES/UNMASKED Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	77.985us	1	1	100.00
V1	smoke	aes_smoke	14.000s	60.883us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	13.000s	69.848us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	231.472us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	655.814us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	218.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	135.444us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	231.472us	20	20	100.00
		aes_csr_aliasing	5.000s	218.137us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	60.883us	50	50	100.00
		aes_config_error	13.000s	134.311us	50	50	100.00
		aes_stress	13.000s	136.379us	50	50	100.00
V2	key_length	aes_smoke	14.000s	60.883us	50	50	100.00
		aes_config_error	13.000s	134.311us	50	50	100.00
		aes_stress	13.000s	136.379us	50	50	100.00
V2	back2back	aes_stress	13.000s	136.379us	50	50	100.00
		aes_b2b	12.000s	178.329us	50	50	100.00
V2	backpressure	aes_stress	13.000s	136.379us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	60.883us	50	50	100.00
		aes_config_error	13.000s	134.311us	50	50	100.00
		aes_stress	13.000s	136.379us	50	50	100.00
		aes_alert_reset	14.000s	220.863us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	80.322us	50	50	100.00
		aes_config_error	13.000s	134.311us	50	50	100.00
		aes_alert_reset	14.000s	220.863us	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	96.980us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	356.225us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	220.863us	50	50	100.00
V2	stress	aes_stress	13.000s	136.379us	50	50	100.00
V2	sideload	aes_stress	13.000s	136.379us	50	50	100.00
		aes_sideload	13.000s	60.407us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	79.028us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	556.391us	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	60.551us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	418.032us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	418.032us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	13.000s	69.848us	5	5	100.00
		aes_csr_rw	8.000s	231.472us	20	20	100.00
		aes_csr_aliasing	5.000s	218.137us	5	5	100.00
		aes_same_csr_outstanding	4.000s	264.237us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	13.000s	69.848us	5	5	100.00
		aes_csr_rw	8.000s	231.472us	20	20	100.00
		aes_csr_aliasing	5.000s	218.137us	5	5	100.00
		aes_same_csr_outstanding	4.000s	264.237us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	14.000s	65.225us	49	50	98.00
V2S	fault_inject	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	191.797us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	191.797us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	191.797us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	191.797us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	300.560us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	2.988ms	5	5	100.00
		aes_tl_intg_err	9.000s	155.529us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	155.529us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	220.863us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	191.797us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	60.883us	50	50	100.00
		aes_stress	13.000s	136.379us	50	50	100.00
		aes_alert_reset	14.000s	220.863us	50	50	100.00
		aes_core_fi	3.200m	10.020ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	191.797us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	83.874us	50	50	100.00
		aes_stress	13.000s	136.379us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	136.379us	50	50	100.00
		aes_sideload	13.000s	60.407us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	83.874us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	83.874us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	83.874us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	83.874us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	83.874us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	136.379us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	136.379us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	75.507us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
		aes_ctr_fi	8.000s	165.902us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	75.507us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	31.534ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	75.507us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_ctr_fi	8.000s	165.902us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
		aes_ctr_fi	8.000s	165.902us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	220.863us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
		aes_ctr_fi	8.000s	165.902us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
		aes_ctr_fi	8.000s	165.902us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_ctr_fi	8.000s	165.902us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	75.507us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	287	300	95.67
		aes_cipher_fi	48.000s	31.534ms	324	350	92.57
V2S		TOTAL			937	985	95.13
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.083m	34.362ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	5	45.45
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.46	94.26	98.81	93.68	97.64	93.33	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_control_fi has 6 failures.
  - 24.aes_control_fi.48302497269400859301168419926662063516808208479480931796739055164154083933701
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job ID: smart:81168454-99e5-4e1f-9f68-44cbaeb2ad6c
```
  - 78.aes_control_fi.45604770604572214490643101785348307319446771543732848871184532970850673036117
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  Job ID: smart:609c9e41-e5b0-4d7e-8669-6b5992ab1496
```
  - ... and 4 more failures.
- Test aes_ctr_fi has 1 failures.
  - 28.aes_ctr_fi.86742185439371985542996357175638615278669378741135587538111319716486990990654
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_ctr_fi/latest/run.log
```
  Job ID: smart:80e4c32f-eeba-41c0-8c8b-f162f8779fc6
```
- Test aes_cipher_fi has 15 failures.
  - 30.aes_cipher_fi.109628933780929879059497266091477397701781276040437083718326349144073083723858
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6f67cbcf-bf97-4187-80e6-5e9f7242bb5b
```
  - 43.aes_cipher_fi.71552055032130636994299739776399779680507718745450407751677519186200270406850
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a6f572df-97b2-48be-b880-3958a8ef10a8
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 15.aes_cipher_fi.78140582204633872622501833903252450019658406712179248689823838121051496944050
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012331584 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012331584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_cipher_fi.71639255048982937579324761229132375426647500204991097457514522386803199141680
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002158496 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002158496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.1015510322990279387968625373197346765810195614588727490889253504915126400039
Line 528, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34361668403 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 34361668403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.21264947852223836211142508963737397216236655641919340400327531353310130102118
Line 637, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1243068225 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1243068225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 8.aes_control_fi.63236094048811979398715297290762747133366999039940731203598242864731687187909
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004615266 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004615266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_control_fi.113305340732928292145235690034524106356876800401937804905704527050565359009723
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008280882 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008280882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

2.aes_stress_all_with_rand_reset.33119046776226189497985661026987368010733633736744769681832768016301215862218
Line 875, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 451687801 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 451663991 PS)
  UVM_ERROR @ 451687801 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 451687801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_fi has 1 failures.

13.aes_fi.48143675636559634034625865287065012435399245700120091233758858589640795392633
Line 1750, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 43045906 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 42962573 PS)
  UVM_ERROR @  43045906 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  43045906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

6.aes_stress_all_with_rand_reset.18028745560789900807343166828685349552461063735848910506783203978035323964507
Line 1527, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4138456893 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4138456893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.62611550816960998993691632616455424065664890832732532441903436369935840565388
Line 1953, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2535326714 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2535326714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 14.aes_core_fi.12129828207490994504260164938805279219023259397971301447519653933690016654994
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016772223 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016772223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.aes_core_fi.15693968101401710864911389942329297243580932503460053615504086352645821614517
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010064436 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010064436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 23.aes_core_fi.37312907288933323060153712428949454514771273229032657410705550509026152796643
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051914783 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb0429384) == 0x0
  UVM_INFO @ 10051914783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_core_fi.99143892244508573962110752577113991868476942899225501481083057222843015650822
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020152564 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xed399084) == 0x0
  UVM_INFO @ 10020152564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 46.aes_core_fi.101541107626503520473431976640878891792455358898140942351248902728886365527412
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007185610 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007185610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_core_fi.41326010413000131397493279276185021485299823801029491307030670869001001904164
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012822589 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012822589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

3.aes_stress_all.31433623837439436699542018197715040385192367650714127590404880071593204316526
Line 7229, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 330020179 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 329980179 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 330020179 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 329980179 PS)
  UVM_ERROR @ 330020179 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 19.aes_reseed.94462639611406368161082664379919587884874387068315593101977814162496486438163
    Line 334, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_reseed/latest/run.log
```
  UVM_FATAL @  19969367 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  19969367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```