AES/UNMASKED Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	75.351us	1	1	100.00
V1	smoke	aes_smoke	18.000s	52.135us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	54.200us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	56.455us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	9.364ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	215.078us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	75.134us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	56.455us	20	20	100.00
		aes_csr_aliasing	4.000s	215.078us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	52.135us	50	50	100.00
		aes_config_error	10.000s	169.197us	50	50	100.00
		aes_stress	15.000s	53.754us	50	50	100.00
V2	key_length	aes_smoke	18.000s	52.135us	50	50	100.00
		aes_config_error	10.000s	169.197us	50	50	100.00
		aes_stress	15.000s	53.754us	50	50	100.00
V2	back2back	aes_stress	15.000s	53.754us	50	50	100.00
		aes_b2b	16.000s	1.551ms	50	50	100.00
V2	backpressure	aes_stress	15.000s	53.754us	50	50	100.00
V2	multi_message	aes_smoke	18.000s	52.135us	50	50	100.00
		aes_config_error	10.000s	169.197us	50	50	100.00
		aes_stress	15.000s	53.754us	50	50	100.00
		aes_alert_reset	13.000s	73.598us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	71.934us	50	50	100.00
		aes_config_error	10.000s	169.197us	50	50	100.00
		aes_alert_reset	13.000s	73.598us	50	50	100.00
V2	trigger_clear_test	aes_clear	21.000s	89.234us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	111.267us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	73.598us	50	50	100.00
V2	stress	aes_stress	15.000s	53.754us	50	50	100.00
V2	sideload	aes_stress	15.000s	53.754us	50	50	100.00
		aes_sideload	10.000s	91.485us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	69.534us	50	50	100.00
V2	stress_all	aes_stress_all	46.000s	16.010ms	10	10	100.00
V2	alert_test	aes_alert_test	12.000s	57.303us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	558.112us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	558.112us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	54.200us	5	5	100.00
		aes_csr_rw	8.000s	56.455us	20	20	100.00
		aes_csr_aliasing	4.000s	215.078us	5	5	100.00
		aes_same_csr_outstanding	13.000s	108.843us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	54.200us	5	5	100.00
		aes_csr_rw	8.000s	56.455us	20	20	100.00
		aes_csr_aliasing	4.000s	215.078us	5	5	100.00
		aes_same_csr_outstanding	13.000s	108.843us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	749.289us	50	50	100.00
V2S	fault_inject	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	280.365us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	280.365us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	280.365us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	280.365us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.700m	10.056ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	19.000s	3.784ms	5	5	100.00
		aes_tl_intg_err	15.000s	378.824us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	378.824us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	73.598us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	280.365us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	52.135us	50	50	100.00
		aes_stress	15.000s	53.754us	50	50	100.00
		aes_alert_reset	13.000s	73.598us	50	50	100.00
		aes_core_fi	32.000s	10.014ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	280.365us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	58.923us	50	50	100.00
		aes_stress	15.000s	53.754us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	53.754us	50	50	100.00
		aes_sideload	10.000s	91.485us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	58.923us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	58.923us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	58.923us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	58.923us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	58.923us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	53.754us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	53.754us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	34.000s	92.264us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
		aes_ctr_fi	18.000s	102.584us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	34.000s	92.264us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.003ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	34.000s	92.264us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_ctr_fi	18.000s	102.584us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
		aes_ctr_fi	18.000s	102.584us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	73.598us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
		aes_ctr_fi	18.000s	102.584us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
		aes_ctr_fi	18.000s	102.584us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_ctr_fi	18.000s	102.584us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	34.000s	92.264us	50	50	100.00
		aes_control_fi	51.000s	15.787ms	283	300	94.33
		aes_cipher_fi	47.000s	10.003ms	322	350	92.00
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.150m	28.193ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.23	97.55	94.48	98.81	93.74	97.64	93.33	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_cipher_fi has 13 failures.
  - 4.aes_cipher_fi.13705563863111325957905830780867604804370914079031420489209668608382855697977
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:a50018e6-1fed-44fd-984f-ef11defbe067
```
  - 11.aes_cipher_fi.43521524156603285096974787284219278543142756162272228285465266051181503169776
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:37d1a4a6-d0bf-4b40-a583-eab497b09d7c
```
  - ... and 11 more failures.
- Test aes_control_fi has 9 failures.
  - 69.aes_control_fi.32669795891129150258977505661241528398782282886325633939553608420459470905949
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/69.aes_control_fi/latest/run.log
```
  Job ID: smart:aeae9392-70c9-4d3f-ae70-02f7d0749e4f
```
  - 78.aes_control_fi.5935187963194004084657756432435165836654494406156611287580075575201585716285
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/78.aes_control_fi/latest/run.log
```
  Job ID: smart:92fbc562-6e6e-4171-81d6-8e4b4a7d1682
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 7.aes_cipher_fi.11097590517045780904183628965980530729937087873608354011780599451563811071064
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10018455940 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018455940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_cipher_fi.10953310111370939213209289286898439725057832814417151963939571614039053703671
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013524849 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013524849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 35.aes_control_fi.24378000010985590567508775713789305326743064322656671405137749722379778542666
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005796077 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005796077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 67.aes_control_fi.27699453458180373964062164735592643562948828132944761123824766617722864719769
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/67.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011333482 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011333482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.43518479246144442240762936309262267036916346865142330273319205501501900390420
Line 1612, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 824640516 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 824640516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.24369022804294611027384642839388948477125867143795106144483750858202361854601
Line 1616, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6111792005 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6111792005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.39066986960967698945726062556964592682570913703965716059064071384701231289347
Line 1020, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 665588345 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 665588345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.73350683441813367782632610609976343265463236259159513432919061169086426880078
Line 1035, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 278554286 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 278554286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 26.aes_core_fi.102133177297914567340937687090084652040494405123366522065010448289164092809999
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014277736 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014277736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_core_fi.82910868266981412523070940331567780369584508707831770510804516091095349094703
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10048829306 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048829306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 12.aes_shadow_reg_errors_with_csr_rw.105617484797290576573495281766129696909077972337321010767267120122771106451741
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10056264704 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x5f3d9f84) == 0x0
  UVM_INFO @ 10056264704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 50.aes_cipher_fi.59846795813699423113197673690778048221395423193261153183092263863584114701221
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 64.aes_core_fi.51776504033651649449809349033610322374642618758955084779844955430734388718197
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018661394 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018661394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```