AES/UNMASKED Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	84.700us	1	1	100.00
V1	smoke	aes_smoke	8.000s	70.640us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	88.845us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	53.644us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.898ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	527.124us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	69.553us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	53.644us	20	20	100.00
		aes_csr_aliasing	4.000s	527.124us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	70.640us	50	50	100.00
		aes_config_error	13.000s	108.166us	50	50	100.00
		aes_stress	9.000s	61.659us	50	50	100.00
V2	key_length	aes_smoke	8.000s	70.640us	50	50	100.00
		aes_config_error	13.000s	108.166us	50	50	100.00
		aes_stress	9.000s	61.659us	50	50	100.00
V2	back2back	aes_stress	9.000s	61.659us	50	50	100.00
		aes_b2b	12.000s	113.344us	50	50	100.00
V2	backpressure	aes_stress	9.000s	61.659us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	70.640us	50	50	100.00
		aes_config_error	13.000s	108.166us	50	50	100.00
		aes_stress	9.000s	61.659us	50	50	100.00
		aes_alert_reset	13.000s	196.492us	50	50	100.00
V2	failure_test	aes_man_cfg_err	20.000s	57.931us	50	50	100.00
		aes_config_error	13.000s	108.166us	50	50	100.00
		aes_alert_reset	13.000s	196.492us	50	50	100.00
V2	trigger_clear_test	aes_clear	20.000s	246.051us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	181.738us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	196.492us	50	50	100.00
V2	stress	aes_stress	9.000s	61.659us	50	50	100.00
V2	sideload	aes_stress	9.000s	61.659us	50	50	100.00
		aes_sideload	10.000s	598.744us	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	62.979us	50	50	100.00
V2	stress_all	aes_stress_all	23.000s	1.450ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	81.969us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	85.032us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	85.032us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	88.845us	5	5	100.00
		aes_csr_rw	3.000s	53.644us	20	20	100.00
		aes_csr_aliasing	4.000s	527.124us	5	5	100.00
		aes_same_csr_outstanding	4.000s	114.130us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	88.845us	5	5	100.00
		aes_csr_rw	3.000s	53.644us	20	20	100.00
		aes_csr_aliasing	4.000s	527.124us	5	5	100.00
		aes_same_csr_outstanding	4.000s	114.130us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	94.004us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	57.604us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	57.604us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	57.604us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	57.604us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	104.267us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.355ms	5	5	100.00
		aes_tl_intg_err	5.000s	965.302us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	965.302us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	196.492us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	57.604us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	70.640us	50	50	100.00
		aes_stress	9.000s	61.659us	50	50	100.00
		aes_alert_reset	13.000s	196.492us	50	50	100.00
		aes_core_fi	13.000s	80.991us	70	70	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	57.604us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	54.190us	50	50	100.00
		aes_stress	9.000s	61.659us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	61.659us	50	50	100.00
		aes_sideload	10.000s	598.744us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	54.190us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	54.190us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	54.190us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	54.190us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	54.190us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	61.659us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	61.659us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	418.039us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
		aes_ctr_fi	8.000s	122.400us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	418.039us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	104.995ms	324	350	92.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	418.039us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_ctr_fi	8.000s	122.400us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
		aes_ctr_fi	8.000s	122.400us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	196.492us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
		aes_ctr_fi	8.000s	122.400us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
		aes_ctr_fi	8.000s	122.400us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_ctr_fi	8.000s	122.400us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	418.039us	50	50	100.00
		aes_control_fi	52.000s	10.177ms	276	300	92.00
		aes_cipher_fi	49.000s	104.995ms	324	350	92.57
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	39.000s	3.595ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1542	1602	96.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	9	81.82
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.57	94.52	98.77	93.89	97.64	93.33	98.66	96.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_cipher_fi has 17 failures.
  - 13.aes_cipher_fi.108734870499257943167408746209456448389478462421982046453450013327882845057459
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6c19b8da-70f2-47a1-92e1-beeec8462d96
```
  - 29.aes_cipher_fi.108715175965128793225336125370805975033736648373466775667206732023257962062410
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d53ff722-5ca6-48eb-a787-f94d69fa8680
```
  - ... and 15 more failures.
- Test aes_control_fi has 12 failures.
  - 46.aes_control_fi.79166243228210868860196311756914654098499778755126105280647107834092002742303
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  Job ID: smart:b783de6b-88bb-4f0c-ba54-9039297b8d7e
```
  - 56.aes_control_fi.83708931855418082058722235768634679860075063771559007126376388479032754081221
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  Job ID: smart:02862a90-28e1-47e8-9747-16f7636cbabb
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 1.aes_control_fi.5080169433241632988368240723106802048579328527952110582174311465945355255173
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007100593 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007100593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.aes_control_fi.114896829795955732872399700359235937450572781995008513831454796808996452892388
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011211444 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011211444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 25.aes_cipher_fi.44220211542752243028920600322297254115281636493955859485114949686723319680145
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019303283 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019303283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_cipher_fi.110551448251852614165197150752951856537328577591825007231278773001783105234091
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009903951 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009903951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.76340442687309724338053941911782802105377455939765232022610263545031818953085
Line 2256, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3594589052 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3594589052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.46692406985590127057980504206142839507669380669772356840532678351057677671121
Line 1573, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3951861368 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3951861368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.108568309772075885324832326867346286355564009421063554158765777908441101094729
Line 732, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 430046133 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 430046133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.63299585591457711955710088771190621884694449695600059133381145200959419023341
Line 969, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1643462359 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1643462359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.72913872697281071266350518523964482583432211082122262262367451689122809786866
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  56595995 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  56595995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.aes_stress_all_with_rand_reset.96894250452564853553834964969535746236589489230164134975050368011192903585905
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22075599 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  22075599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 226.aes_cipher_fi.58830777610069908074228614461772908359303195524188169405911616467676562153399
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/226.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```