AES/UNMASKED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 7.000s 64.213us 1 1 100.00
V1 smoke aes_smoke 10.000s 57.614us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 12.000s 115.001us 5 5 100.00
V1 csr_rw aes_csr_rw 8.000s 112.767us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 11.000s 4.002ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 276.169us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 12.000s 67.048us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 8.000s 112.767us 20 20 100.00
aes_csr_aliasing 5.000s 276.169us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 10.000s 57.614us 50 50 100.00
aes_config_error 14.000s 287.160us 50 50 100.00
aes_stress 14.000s 102.085us 50 50 100.00
V2 key_length aes_smoke 10.000s 57.614us 50 50 100.00
aes_config_error 14.000s 287.160us 50 50 100.00
aes_stress 14.000s 102.085us 50 50 100.00
V2 back2back aes_stress 14.000s 102.085us 50 50 100.00
aes_b2b 15.000s 130.255us 50 50 100.00
V2 backpressure aes_stress 14.000s 102.085us 50 50 100.00
V2 multi_message aes_smoke 10.000s 57.614us 50 50 100.00
aes_config_error 14.000s 287.160us 50 50 100.00
aes_stress 14.000s 102.085us 50 50 100.00
aes_alert_reset 13.000s 85.631us 49 50 98.00
V2 failure_test aes_man_cfg_err 18.000s 78.779us 50 50 100.00
aes_config_error 14.000s 287.160us 50 50 100.00
aes_alert_reset 13.000s 85.631us 49 50 98.00
V2 trigger_clear_test aes_clear 10.000s 82.649us 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 6.000s 1.449ms 1 1 100.00
V2 reset_recovery aes_alert_reset 13.000s 85.631us 49 50 98.00
V2 stress aes_stress 14.000s 102.085us 50 50 100.00
V2 sideload aes_stress 14.000s 102.085us 50 50 100.00
aes_sideload 14.000s 62.581us 50 50 100.00
V2 deinitialization aes_deinit 14.000s 70.287us 50 50 100.00
V2 stress_all aes_stress_all 33.000s 2.088ms 10 10 100.00
V2 alert_test aes_alert_test 8.000s 57.528us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 15.000s 151.649us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 15.000s 151.649us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 12.000s 115.001us 5 5 100.00
aes_csr_rw 8.000s 112.767us 20 20 100.00
aes_csr_aliasing 5.000s 276.169us 5 5 100.00
aes_same_csr_outstanding 8.000s 105.238us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 12.000s 115.001us 5 5 100.00
aes_csr_rw 8.000s 112.767us 20 20 100.00
aes_csr_aliasing 5.000s 276.169us 5 5 100.00
aes_same_csr_outstanding 8.000s 105.238us 20 20 100.00
V2 TOTAL 500 501 99.80
V2S reseeding aes_reseed 14.000s 86.978us 50 50 100.00
V2S fault_inject aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
V2S shadow_reg_update_error aes_shadow_reg_errors 8.000s 85.765us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 8.000s 85.765us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 8.000s 85.765us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 8.000s 85.765us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 12.000s 119.155us 20 20 100.00
V2S tl_intg_err aes_sec_cm 6.000s 4.321ms 5 5 100.00
aes_tl_intg_err 15.000s 171.086us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 15.000s 171.086us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 13.000s 85.631us 49 50 98.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 8.000s 85.765us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 10.000s 57.614us 50 50 100.00
aes_stress 14.000s 102.085us 50 50 100.00
aes_alert_reset 13.000s 85.631us 49 50 98.00
aes_core_fi 42.000s 10.005ms 65 70 92.86
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 8.000s 85.765us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 13.000s 90.983us 50 50 100.00
aes_stress 14.000s 102.085us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 14.000s 102.085us 50 50 100.00
aes_sideload 14.000s 62.581us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 13.000s 90.983us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 13.000s 90.983us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 13.000s 90.983us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 13.000s 90.983us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 13.000s 90.983us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 14.000s 102.085us 50 50 100.00
V2S sec_cm_key_masking aes_stress 14.000s 102.085us 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 14.000s 361.163us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
aes_ctr_fi 13.000s 58.691us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 14.000s 361.163us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 49.000s 32.177ms 329 350 94.00
V2S sec_cm_ctr_fsm_sparse aes_fi 14.000s 361.163us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_ctr_fi 13.000s 58.691us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
aes_ctr_fi 13.000s 58.691us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 13.000s 85.631us 49 50 98.00
V2S sec_cm_main_fsm_local_esc aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
aes_ctr_fi 13.000s 58.691us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
aes_ctr_fi 13.000s 58.691us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_ctr_fi 13.000s 58.691us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 14.000s 361.163us 50 50 100.00
aes_control_fi 46.000s 75.025ms 279 300 93.00
aes_cipher_fi 49.000s 32.177ms 329 350 94.00
V2S TOTAL 938 985 95.23
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 4.200m 9.294ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1544 1602 96.38

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 12 92.31
V2S 11 11 8 72.73
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.15 97.48 94.31 98.77 93.65 97.72 91.11 98.85 95.41

Failure Buckets

Past Results