AES/UNMASKED Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	7.000s	64.213us	1	1	100.00
V1	smoke	aes_smoke	10.000s	57.614us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	12.000s	115.001us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	112.767us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	4.002ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	276.169us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	12.000s	67.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	112.767us	20	20	100.00
		aes_csr_aliasing	5.000s	276.169us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	57.614us	50	50	100.00
		aes_config_error	14.000s	287.160us	50	50	100.00
		aes_stress	14.000s	102.085us	50	50	100.00
V2	key_length	aes_smoke	10.000s	57.614us	50	50	100.00
		aes_config_error	14.000s	287.160us	50	50	100.00
		aes_stress	14.000s	102.085us	50	50	100.00
V2	back2back	aes_stress	14.000s	102.085us	50	50	100.00
		aes_b2b	15.000s	130.255us	50	50	100.00
V2	backpressure	aes_stress	14.000s	102.085us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	57.614us	50	50	100.00
		aes_config_error	14.000s	287.160us	50	50	100.00
		aes_stress	14.000s	102.085us	50	50	100.00
		aes_alert_reset	13.000s	85.631us	49	50	98.00
V2	failure_test	aes_man_cfg_err	18.000s	78.779us	50	50	100.00
		aes_config_error	14.000s	287.160us	50	50	100.00
		aes_alert_reset	13.000s	85.631us	49	50	98.00
V2	trigger_clear_test	aes_clear	10.000s	82.649us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	1.449ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	85.631us	49	50	98.00
V2	stress	aes_stress	14.000s	102.085us	50	50	100.00
V2	sideload	aes_stress	14.000s	102.085us	50	50	100.00
		aes_sideload	14.000s	62.581us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	70.287us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	2.088ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	57.528us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	151.649us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	151.649us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	12.000s	115.001us	5	5	100.00
		aes_csr_rw	8.000s	112.767us	20	20	100.00
		aes_csr_aliasing	5.000s	276.169us	5	5	100.00
		aes_same_csr_outstanding	8.000s	105.238us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	12.000s	115.001us	5	5	100.00
		aes_csr_rw	8.000s	112.767us	20	20	100.00
		aes_csr_aliasing	5.000s	276.169us	5	5	100.00
		aes_same_csr_outstanding	8.000s	105.238us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	14.000s	86.978us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	85.765us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	85.765us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	85.765us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	85.765us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	12.000s	119.155us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	4.321ms	5	5	100.00
		aes_tl_intg_err	15.000s	171.086us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	15.000s	171.086us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	85.631us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	85.765us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	57.614us	50	50	100.00
		aes_stress	14.000s	102.085us	50	50	100.00
		aes_alert_reset	13.000s	85.631us	49	50	98.00
		aes_core_fi	42.000s	10.005ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	85.765us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	90.983us	50	50	100.00
		aes_stress	14.000s	102.085us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	102.085us	50	50	100.00
		aes_sideload	14.000s	62.581us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	90.983us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	90.983us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	90.983us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	90.983us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	90.983us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	102.085us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	102.085us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	361.163us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
		aes_ctr_fi	13.000s	58.691us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	361.163us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	32.177ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	361.163us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_ctr_fi	13.000s	58.691us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
		aes_ctr_fi	13.000s	58.691us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	85.631us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
		aes_ctr_fi	13.000s	58.691us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
		aes_ctr_fi	13.000s	58.691us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_ctr_fi	13.000s	58.691us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	361.163us	50	50	100.00
		aes_control_fi	46.000s	75.025ms	279	300	93.00
		aes_cipher_fi	49.000s	32.177ms	329	350	94.00
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.200m	9.294ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1544	1602	96.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.48	94.31	98.77	93.65	97.72	91.11	98.85	95.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
- Test aes_cipher_fi has 15 failures.
  - 2.aes_cipher_fi.88930518445442607080868700345377738891596492633897908638359883635928079477233
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c22437c4-7fc7-4594-9b76-a4da8ea6394c
```
  - 6.aes_cipher_fi.1190742024304606918951918559426805629658296469075561456172481062598564725289
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job ID: smart:eeeaea3d-9f9d-41dd-8b87-7be5f284cdff
```
  - ... and 13 more failures.
- Test aes_control_fi has 8 failures.
  - 70.aes_control_fi.95573396067340341824907051794996967222954695464459898537592965785722776917678
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/70.aes_control_fi/latest/run.log
```
  Job ID: smart:c2af4a2a-8e12-4534-8c00-bab89679a1c0
```
  - 71.aes_control_fi.43906708370637594130397564226165094679713471718085815030217925058609791735701
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_control_fi/latest/run.log
```
  Job ID: smart:2007c7dd-f8c9-46d9-ba0c-dab75e5d113e
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 3.aes_control_fi.101895395427816700373509039007922026832466057612875100040029654888611297622427
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010857620 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010857620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_control_fi.86091483693220933117487836322035381075354254208548146470288117232738444967999
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013202072 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013202072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 27.aes_cipher_fi.108963825439538520986655514662388327789071556722049067634696569898810403465239
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007887925 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007887925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.aes_cipher_fi.79568716419332059953657261657964762278894622510186247993020778040165888584719
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019059624 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019059624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.107729893252043089946756994101252802795748314464451684822370676289851575146730
Line 1617, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 417579164 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 417579164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.30467752886174843803664069675896189344260854975778175564111182029894829170715
Line 1465, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 450180500 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 450180500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.21634297252625865501470717336257529359791307851575912993258866036435387807810
Line 845, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 492408779 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 492408779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.76504587057413858921604207791171344304932623487444285401884380209312026494674
Line 931, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 413249293 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 413249293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 2.aes_core_fi.51878931108498660764241338022188519835807526721634883327925427321040071454024
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002911396 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002911396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_core_fi.111443802511380747666047509497296892108340402594883029885126965285620563911341
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010892137 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010892137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 11.aes_core_fi.21707430437599951436042582237812578680059709438488059571768524965541004452606
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10030759543 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10030759543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 32.aes_alert_reset.17696223227986469416217882459092003889701567137438311385411879578729258744227
    Line 879, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 39704977 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 39649421 PS)
  UVM_ERROR @  39704977 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  39704977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```