AES/UNMASKED Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	98.173us	1	1	100.00
V1	smoke	aes_smoke	11.000s	674.268us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	68.155us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	160.147us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	961.932us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	175.509us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	53.139us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	160.147us	20	20	100.00
		aes_csr_aliasing	5.000s	175.509us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	674.268us	50	50	100.00
		aes_config_error	23.000s	114.474us	50	50	100.00
		aes_stress	14.000s	57.451us	50	50	100.00
V2	key_length	aes_smoke	11.000s	674.268us	50	50	100.00
		aes_config_error	23.000s	114.474us	50	50	100.00
		aes_stress	14.000s	57.451us	50	50	100.00
V2	back2back	aes_stress	14.000s	57.451us	50	50	100.00
		aes_b2b	19.000s	135.195us	50	50	100.00
V2	backpressure	aes_stress	14.000s	57.451us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	674.268us	50	50	100.00
		aes_config_error	23.000s	114.474us	50	50	100.00
		aes_stress	14.000s	57.451us	50	50	100.00
		aes_alert_reset	14.000s	332.931us	50	50	100.00
V2	failure_test	aes_man_cfg_err	17.000s	84.788us	50	50	100.00
		aes_config_error	23.000s	114.474us	50	50	100.00
		aes_alert_reset	14.000s	332.931us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	258.054us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	565.193us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	332.931us	50	50	100.00
V2	stress	aes_stress	14.000s	57.451us	50	50	100.00
V2	sideload	aes_stress	14.000s	57.451us	50	50	100.00
		aes_sideload	14.000s	144.326us	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	62.385us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	11.659ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	81.569us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	347.289us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	347.289us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	68.155us	5	5	100.00
		aes_csr_rw	4.000s	160.147us	20	20	100.00
		aes_csr_aliasing	5.000s	175.509us	5	5	100.00
		aes_same_csr_outstanding	7.000s	84.098us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	68.155us	5	5	100.00
		aes_csr_rw	4.000s	160.147us	20	20	100.00
		aes_csr_aliasing	5.000s	175.509us	5	5	100.00
		aes_same_csr_outstanding	7.000s	84.098us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	15.000s	651.113us	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	182.347us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	182.347us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	182.347us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	182.347us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	714.779us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.343ms	5	5	100.00
		aes_tl_intg_err	6.000s	1.429ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.429ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	332.931us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	182.347us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	674.268us	50	50	100.00
		aes_stress	14.000s	57.451us	50	50	100.00
		aes_alert_reset	14.000s	332.931us	50	50	100.00
		aes_core_fi	56.000s	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	182.347us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	59.445us	50	50	100.00
		aes_stress	14.000s	57.451us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	57.451us	50	50	100.00
		aes_sideload	14.000s	144.326us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	59.445us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	59.445us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	59.445us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	59.445us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	59.445us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	57.451us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	57.451us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	128.178us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
		aes_ctr_fi	15.000s	55.166us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	128.178us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	29.751ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	128.178us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_ctr_fi	15.000s	55.166us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
		aes_ctr_fi	15.000s	55.166us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	332.931us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
		aes_ctr_fi	15.000s	55.166us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
		aes_ctr_fi	15.000s	55.166us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_ctr_fi	15.000s	55.166us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	128.178us	48	50	96.00
		aes_control_fi	43.000s	10.017ms	273	300	91.00
		aes_cipher_fi	50.000s	29.751ms	328	350	93.71
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	13.733m	54.124ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.52	94.39	98.77	93.45	97.64	91.11	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_cipher_fi has 14 failures.
  - 2.aes_cipher_fi.91468849377492277103751152020240484330649799969387972777640358393677499105953
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c402f6be-2be4-425a-b9ce-b051075cb6f2
```
  - 5.aes_cipher_fi.39386979489563137427712291902703039624659352958796679671683269667033749079973
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job ID: smart:dcb45777-fef2-40f4-8d51-22410d01ac09
```
  - ... and 12 more failures.
- Test aes_control_fi has 16 failures.
  - 4.aes_control_fi.106398519310129344952529484976255393602434687963758506268654671262487268402930
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:cc076498-42c2-4889-9708-68aa45837e02
```
  - 57.aes_control_fi.43669967311679977385996700312389001135720789161649807646531445462350998810949
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  Job ID: smart:a010308e-d8b7-497f-8e6a-95e4a402216d
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 8.aes_control_fi.7702979824152223756697447418177506099919183091920387806762305423697478327642
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005014676 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005014676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_control_fi.76483592576820494494495606388940634749723313719895544662412079193729239303554
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009510319 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009510319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 52.aes_cipher_fi.2557981204352017413568815936713967141354964713810226393659237087284079801449
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006021113 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006021113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.aes_cipher_fi.102945885859582963934552123612876507056653884729938449679495026899322769459341
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008544416 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008544416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.62171631319374943666829187714360354407218220268335917688658774732232813165489
Line 1214, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2831216177 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2831216177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.87076833995748152743416050986456690621575333074473731456406941300664473264636
Line 979, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 973157827 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 973157827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.95531233672859979397695746140789115500797686639483248579225411097371958017275
Line 1498, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1062479792 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1062479792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.42067141218775936891119963661677972584561856840750564592510354325365167875531
Line 1098, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 50340956472 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 50340956472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 19.aes_core_fi.42510125445549406375534779938014994919850050659891815878158500668683658962663
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039898110 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039898110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 55.aes_core_fi.96198610106535272298073705317962163722277688345459977255209072796488521153061
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011609261 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011609261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

26.aes_fi.18400808273780905571400408819438688943906570114490568737213216982858035908122
Line 3047, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 11838508 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 11828091 PS)
  UVM_ERROR @  11838508 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  11838508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.aes_fi.34778126947558818433511992424249874200657038375973538822106916289224573044644
Line 597, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 5025739 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 5015638 PS)
  UVM_ERROR @   5025739 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   5025739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 52.aes_core_fi.103793801541525146879803944191154184166866223777728266032645770956992379391535
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004724267 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004724267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 159.aes_cipher_fi.106524029484020601806231459433162821088670447872932872637452932177071053138322
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/159.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @   8955765 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   8955765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```