AES/UNMASKED Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	53.319us	1	1	100.00
V1	smoke	aes_smoke	10.000s	309.778us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	84.530us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	124.465us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	328.155us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	87.546us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	69.860us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	124.465us	20	20	100.00
		aes_csr_aliasing	5.000s	87.546us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	10.000s	309.778us	50	50	100.00
		aes_config_error	14.000s	63.022us	50	50	100.00
		aes_stress	9.000s	90.289us	50	50	100.00
V2	key_length	aes_smoke	10.000s	309.778us	50	50	100.00
		aes_config_error	14.000s	63.022us	50	50	100.00
		aes_stress	9.000s	90.289us	50	50	100.00
V2	back2back	aes_stress	9.000s	90.289us	50	50	100.00
		aes_b2b	14.000s	115.703us	50	50	100.00
V2	backpressure	aes_stress	9.000s	90.289us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	309.778us	50	50	100.00
		aes_config_error	14.000s	63.022us	50	50	100.00
		aes_stress	9.000s	90.289us	50	50	100.00
		aes_alert_reset	9.000s	193.438us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	69.033us	50	50	100.00
		aes_config_error	14.000s	63.022us	50	50	100.00
		aes_alert_reset	9.000s	193.438us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	165.922us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	815.929us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	193.438us	50	50	100.00
V2	stress	aes_stress	9.000s	90.289us	50	50	100.00
V2	sideload	aes_stress	9.000s	90.289us	50	50	100.00
		aes_sideload	12.000s	521.230us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	80.949us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	4.916ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	63.587us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	123.910us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	123.910us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	84.530us	5	5	100.00
		aes_csr_rw	3.000s	124.465us	20	20	100.00
		aes_csr_aliasing	5.000s	87.546us	5	5	100.00
		aes_same_csr_outstanding	46.000s	10.070ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	84.530us	5	5	100.00
		aes_csr_rw	3.000s	124.465us	20	20	100.00
		aes_csr_aliasing	5.000s	87.546us	5	5	100.00
		aes_same_csr_outstanding	46.000s	10.070ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	14.000s	75.320us	49	50	98.00
V2S	fault_inject	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	81.199us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	81.199us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	81.199us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	81.199us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	80.741us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	3.381ms	5	5	100.00
		aes_tl_intg_err	5.000s	390.893us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	390.893us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	193.438us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	81.199us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	309.778us	50	50	100.00
		aes_stress	9.000s	90.289us	50	50	100.00
		aes_alert_reset	9.000s	193.438us	50	50	100.00
		aes_core_fi	43.000s	10.002ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	81.199us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	58.386us	50	50	100.00
		aes_stress	9.000s	90.289us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	90.289us	50	50	100.00
		aes_sideload	12.000s	521.230us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	58.386us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	58.386us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	58.386us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	58.386us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	58.386us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	90.289us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	90.289us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	269.812us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
		aes_ctr_fi	7.000s	74.515us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	269.812us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	17.347ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	269.812us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_ctr_fi	7.000s	74.515us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
		aes_ctr_fi	7.000s	74.515us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	193.438us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
		aes_ctr_fi	7.000s	74.515us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
		aes_ctr_fi	7.000s	74.515us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_ctr_fi	7.000s	74.515us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	269.812us	50	50	100.00
		aes_control_fi	49.000s	65.652ms	277	300	92.33
		aes_cipher_fi	45.000s	17.347ms	323	350	92.29
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	34.000s	2.237ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.07	97.37	94.05	98.71	93.48	97.72	91.11	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 39 failures:
- Test aes_cipher_fi has 18 failures.
  - 4.aes_cipher_fi.95102495442873272583003205820834071417052818902056078322350689478776928812483
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f01af8af-0755-4dd5-bc54-79763bbcec60
```
  - 30.aes_cipher_fi.42682553513876614421048241550306035890779950263978561805123175044437629726686
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cd36a30f-93fe-4593-aa3f-30017f4a9215
```
  - ... and 16 more failures.
- Test aes_ctr_fi has 1 failures.
  - 29.aes_ctr_fi.103878924424692965919259774774961508797014177620685867243887783739430665507516
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_ctr_fi/latest/run.log
```
  Job ID: smart:921e368f-9ed6-422d-8a98-9eaf7fdf028e
```
- Test aes_control_fi has 20 failures.
  - 35.aes_control_fi.29769771732462049711625456697359943561591790535789318787200152268047586713289
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:60f9da6d-575c-452d-aa18-a588f4de4fbf
```
  - 55.aes_control_fi.62106214782104847234567107765379956931860054791177275679339056963028397635798
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  Job ID: smart:48e70dbe-2808-4e22-bb3e-740fbf36b5c3
```
  - ... and 18 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 15.aes_cipher_fi.38292614893308045567085472032800207952841623308698354766606838215356400735989
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005422119 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005422119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.aes_cipher_fi.8575149033688839283182733631045876628292272760823151168116545726551576853513
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003879899 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003879899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.24932457713029504435865190051259135947793589386328486829756541392136282607500
Line 2060, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2237020607 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2237020607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.51239769869104664537072579743269909400997302393377116268085647364515918684596
Line 628, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 245792580 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 245792580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.41258885355559422212998749664933030431525492918550245543328553233871847909620
Line 1124, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2841849936 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2841849936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.83594941613513926450270423248032072027425171013139911773783483901939268618726
Line 709, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 636935215 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 636935215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 6.aes_control_fi.71669934214069305901110363010905257256581317128835380605274868556081776724368
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012566962 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012566962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 128.aes_control_fi.45878811882480924057683582675999016419979816273133573721877725905022722088377
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/128.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013497079 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013497079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 3.aes_reseed.1910340902361454836042691047346962297951164885991888179027740859760268547161
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_reseed/latest/run.log
```
  UVM_FATAL @  16056216 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  16056216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.53328502343974986176455464696049054502278591913950338682599875382265576728347
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26415836 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  26415836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 17.aes_same_csr_outstanding.3794599944421996542204831426457029456977210686575279736436509809833062772073
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10070354409 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x37dd8484) == 0x0
  UVM_INFO @ 10070354409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.aes_csr_mem_rw_with_rand_reset.11760908206808229800045867623904655450210533125412585147206521355406987421904
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 122420975 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 122420975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.3646780942452688564137353619368814236176245616590774065579171205992286796221
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002341000 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002341000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```