AES/UNMASKED Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	159.155us	1	1	100.00
V1	smoke	aes_smoke	9.000s	100.865us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.452us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	54.840us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.920ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	223.896us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	167.785us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	54.840us	20	20	100.00
		aes_csr_aliasing	5.000s	223.896us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	100.865us	50	50	100.00
		aes_config_error	14.000s	582.770us	50	50	100.00
		aes_stress	13.000s	121.807us	50	50	100.00
V2	key_length	aes_smoke	9.000s	100.865us	50	50	100.00
		aes_config_error	14.000s	582.770us	50	50	100.00
		aes_stress	13.000s	121.807us	50	50	100.00
V2	back2back	aes_stress	13.000s	121.807us	50	50	100.00
		aes_b2b	10.000s	375.465us	50	50	100.00
V2	backpressure	aes_stress	13.000s	121.807us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	100.865us	50	50	100.00
		aes_config_error	14.000s	582.770us	50	50	100.00
		aes_stress	13.000s	121.807us	50	50	100.00
		aes_alert_reset	14.000s	72.990us	50	50	100.00
V2	failure_test	aes_man_cfg_err	17.000s	59.017us	50	50	100.00
		aes_config_error	14.000s	582.770us	50	50	100.00
		aes_alert_reset	14.000s	72.990us	50	50	100.00
V2	trigger_clear_test	aes_clear	11.000s	327.499us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	432.519us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	72.990us	50	50	100.00
V2	stress	aes_stress	13.000s	121.807us	50	50	100.00
V2	sideload	aes_stress	13.000s	121.807us	50	50	100.00
		aes_sideload	13.000s	95.286us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	131.002us	50	50	100.00
V2	stress_all	aes_stress_all	27.000s	2.548ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	63.457us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	339.952us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	339.952us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.452us	5	5	100.00
		aes_csr_rw	3.000s	54.840us	20	20	100.00
		aes_csr_aliasing	5.000s	223.896us	5	5	100.00
		aes_same_csr_outstanding	4.000s	293.114us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.452us	5	5	100.00
		aes_csr_rw	3.000s	54.840us	20	20	100.00
		aes_csr_aliasing	5.000s	223.896us	5	5	100.00
		aes_same_csr_outstanding	4.000s	293.114us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	65.999us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	73.396us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	73.396us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	73.396us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	73.396us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	267.597us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.510ms	5	5	100.00
		aes_tl_intg_err	5.000s	171.109us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	171.109us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	72.990us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	73.396us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	100.865us	50	50	100.00
		aes_stress	13.000s	121.807us	50	50	100.00
		aes_alert_reset	14.000s	72.990us	50	50	100.00
		aes_core_fi	57.000s	10.073ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	73.396us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	7.000s	125.344us	50	50	100.00
		aes_stress	13.000s	121.807us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	121.807us	50	50	100.00
		aes_sideload	13.000s	95.286us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	7.000s	125.344us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	7.000s	125.344us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	7.000s	125.344us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	7.000s	125.344us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	7.000s	125.344us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	121.807us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	121.807us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	342.098us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
		aes_ctr_fi	8.000s	58.454us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	342.098us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	32.166ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	342.098us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_ctr_fi	8.000s	58.454us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
		aes_ctr_fi	8.000s	58.454us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	72.990us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
		aes_ctr_fi	8.000s	58.454us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
		aes_ctr_fi	8.000s	58.454us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_ctr_fi	8.000s	58.454us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	342.098us	49	50	98.00
		aes_control_fi	52.000s	36.652ms	279	300	93.00
		aes_cipher_fi	43.000s	32.166ms	329	350	94.00
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.467m	14.065ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1545	1602	96.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.23	97.55	94.48	98.81	93.80	97.64	93.33	98.66	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_cipher_fi has 16 failures.
  - 0.aes_cipher_fi.56036631740125870034328732677604842248279993601225189956569075318763477296355
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c4df4662-970b-4cfa-b2de-1caf0f333cda
```
  - 2.aes_cipher_fi.100566330891662595142216787568859114139183959157248272450464138259837861286825
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:537bc1a8-6ec6-48c7-ae6d-c282a464f6b5
```
  - ... and 14 more failures.
- Test aes_control_fi has 14 failures.
  - 4.aes_control_fi.93629334091473426619519829180018343064429735564673957565969703348757249006205
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:c432786c-c862-4f6e-a50f-bd17da839c82
```
  - 20.aes_control_fi.68048855866792762145298414351779651015778307544375723101161097516997559086362
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:e542cbd2-c93d-4f4f-98f7-c33260b36764
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 77.aes_control_fi.22226521513116067233246117196473957199133391859946125924862636148514625053574
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/77.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010903671 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010903671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 82.aes_control_fi.10022053072247979240754338687201897774535251443419538962161979434637741429185
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/82.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017387192 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017387192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.95218945124568333469693295316507239128340665317544303459722387578329858359575
Line 911, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 794786679 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 794786679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.16408506662978752565239703538099627933459014203453274452937785118770877064642
Line 1180, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3380723352 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3380723352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.23841774671271279889790360308368362330898480533661344235532672914869813087086
Line 850, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1525858069 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1525858069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.30619481525271877606937536376788955081207108161364728600562081992738058786212
Line 935, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14064543003 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 14064543003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 30.aes_cipher_fi.19591224155023487095428726385082385435482880765168561145002933301335755364987
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009034114 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009034114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 69.aes_cipher_fi.29330504223017822509441066219948737539756979446836719940026385324641447202687
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/69.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013985874 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013985874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 15.aes_core_fi.85499878638575902303660419350667620226535318943585768145070689660731486332570
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005531920 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005531920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.101102601130149069720023898882040366557644547722617127732263882179789239121871
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006201324 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006201324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 29.aes_core_fi.20840277468139579270764044121544046446207946826073296050909545590254175383962
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10073305956 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x552fdc84) == 0x0
  UVM_INFO @ 10073305956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 44.aes_fi.53266801090781250509705512648523400409444642475795951883394676528017929160093
    Line 4259, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_fi/latest/run.log
```
  UVM_FATAL @  76239305 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  76239305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.103971642297532154235271366915132711670622316947629917934791147015079585846530
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021442938 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021442938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 156.aes_cipher_fi.25822618445952053848481838389433735879591424970014992788322585771692705181911
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/156.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  19087394 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  19087394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```