AES/UNMASKED Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	203.232us	1	1	100.00
V1	smoke	aes_smoke	11.000s	63.916us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	77.782us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	55.596us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	1.008ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	88.897us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	81.632us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	55.596us	20	20	100.00
		aes_csr_aliasing	5.000s	88.897us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	63.916us	50	50	100.00
		aes_config_error	10.000s	470.877us	50	50	100.00
		aes_stress	19.000s	141.226us	50	50	100.00
V2	key_length	aes_smoke	11.000s	63.916us	50	50	100.00
		aes_config_error	10.000s	470.877us	50	50	100.00
		aes_stress	19.000s	141.226us	50	50	100.00
V2	back2back	aes_stress	19.000s	141.226us	50	50	100.00
		aes_b2b	17.000s	386.146us	50	50	100.00
V2	backpressure	aes_stress	19.000s	141.226us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	63.916us	50	50	100.00
		aes_config_error	10.000s	470.877us	50	50	100.00
		aes_stress	19.000s	141.226us	50	50	100.00
		aes_alert_reset	13.000s	320.041us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	79.317us	50	50	100.00
		aes_config_error	10.000s	470.877us	50	50	100.00
		aes_alert_reset	13.000s	320.041us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	178.618us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	208.302us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	320.041us	50	50	100.00
V2	stress	aes_stress	19.000s	141.226us	50	50	100.00
V2	sideload	aes_stress	19.000s	141.226us	50	50	100.00
		aes_sideload	14.000s	144.521us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	181.512us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	1.264ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	50.600us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	71.995us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	71.995us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	77.782us	5	5	100.00
		aes_csr_rw	7.000s	55.596us	20	20	100.00
		aes_csr_aliasing	5.000s	88.897us	5	5	100.00
		aes_same_csr_outstanding	5.000s	100.910us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	77.782us	5	5	100.00
		aes_csr_rw	7.000s	55.596us	20	20	100.00
		aes_csr_aliasing	5.000s	88.897us	5	5	100.00
		aes_same_csr_outstanding	5.000s	100.910us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	18.000s	696.754us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	72.702us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	72.702us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	72.702us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	72.702us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	253.036us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.179ms	5	5	100.00
		aes_tl_intg_err	6.000s	184.844us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	184.844us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	320.041us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	72.702us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	63.916us	50	50	100.00
		aes_stress	19.000s	141.226us	50	50	100.00
		aes_alert_reset	13.000s	320.041us	50	50	100.00
		aes_core_fi	6.717m	10.007ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	72.702us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	60.600us	50	50	100.00
		aes_stress	19.000s	141.226us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	19.000s	141.226us	50	50	100.00
		aes_sideload	14.000s	144.521us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	60.600us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	60.600us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	60.600us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	60.600us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	60.600us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	19.000s	141.226us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	19.000s	141.226us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	327.617us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
		aes_ctr_fi	18.000s	78.012us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	327.617us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	65.632ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	327.617us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_ctr_fi	18.000s	78.012us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
		aes_ctr_fi	18.000s	78.012us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	320.041us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
		aes_ctr_fi	18.000s	78.012us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
		aes_ctr_fi	18.000s	78.012us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_ctr_fi	18.000s	78.012us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	327.617us	49	50	98.00
		aes_control_fi	45.000s	63.028ms	277	300	92.33
		aes_cipher_fi	46.000s	65.632ms	326	350	93.14
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.700m	18.931ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.50	94.35	98.81	93.60	97.64	93.33	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
- Test aes_control_fi has 14 failures.
  - 1.aes_control_fi.80690307434558401313847796927018849167654111697050970269268569726192551530044
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job ID: smart:ffa787fc-93e3-4baf-a826-589ad523defc
```
  - 13.aes_control_fi.7797904028175755379225714585602583568095989790220411875375681109245070204737
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:7917a287-accf-4089-b0cb-5709908e4083
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 12 failures.
  - 28.aes_cipher_fi.34718103908889633322772815344152550212361068455148256370957821494162056724124
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3a956ead-6c05-4e2f-8f42-e9fd66971ec6
```
  - 40.aes_cipher_fi.113227166279891859288308278344812272212092917249152458359799546665031613416177
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job ID: smart:75b8d3ab-cdd3-479a-b610-a7a206a3020f
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 6.aes_cipher_fi.37009927802079598857280987521799173476106334132832119070211196299876513211555
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016924064 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016924064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_cipher_fi.36736108352124530018286962920501294204217329573703743851633396217089199312001
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010083582 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010083582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 19.aes_control_fi.51129020284313199539765542844631859178436651397400707287815581433981639298733
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015921889 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015921889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 62.aes_control_fi.68953777200395418433632180382001926697477100527774024250649558321184095308224
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007397629 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007397629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

2.aes_stress_all_with_rand_reset.40751632170152768223178559205744944790847374726132641887387364253751442370246
Line 1120, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 551624122 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 551624122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.33633493077808668539814132749005383591869498057761277444517492969095378193798
Line 395, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 795143985 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 795143985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.98820153188999020122125555065661994382012054459502942283059686020715008496409
Line 1476, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 592970358 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 592970358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.22129325237142175239367108870384518995606456101337570461770909171693858843350
Line 1545, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4008748572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4008748572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.24847253936217000815643485069571175354354536635273566309201304253543286791985
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004910056 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004910056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_core_fi.23069607605858327270425072010241185190186995018441258348710838552972511633626
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006661835 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006661835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 19.aes_core_fi.115143236509870701887856991712008501883393112767500616378337329514323072041641
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006986075 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xcf606484) == 0x0
  UVM_INFO @ 10006986075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_core_fi.87561622291582348768028175160092787792157139054751600857764418595780030470424
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051237648 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x17477084) == 0x0
  UVM_INFO @ 10051237648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 1.aes_fi.101197026881730623377872936544990454014635483770815325017454957009599456755240
    Line 2762, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 15217960 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 15197552 PS)
  UVM_ERROR @  15217960 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  15217960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```