AES/UNMASKED Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	61.889us	1	1	100.00
V1	smoke	aes_smoke	13.000s	59.614us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	80.043us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	72.928us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	612.590us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	87.051us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	70.255us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	72.928us	20	20	100.00
		aes_csr_aliasing	5.000s	87.051us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	13.000s	59.614us	50	50	100.00
		aes_config_error	19.000s	256.439us	50	50	100.00
		aes_stress	13.000s	91.470us	50	50	100.00
V2	key_length	aes_smoke	13.000s	59.614us	50	50	100.00
		aes_config_error	19.000s	256.439us	50	50	100.00
		aes_stress	13.000s	91.470us	50	50	100.00
V2	back2back	aes_stress	13.000s	91.470us	50	50	100.00
		aes_b2b	15.000s	286.768us	50	50	100.00
V2	backpressure	aes_stress	13.000s	91.470us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	59.614us	50	50	100.00
		aes_config_error	19.000s	256.439us	50	50	100.00
		aes_stress	13.000s	91.470us	50	50	100.00
		aes_alert_reset	14.000s	744.868us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	54.840us	50	50	100.00
		aes_config_error	19.000s	256.439us	50	50	100.00
		aes_alert_reset	14.000s	744.868us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	97.636us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	329.944us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	744.868us	50	50	100.00
V2	stress	aes_stress	13.000s	91.470us	50	50	100.00
V2	sideload	aes_stress	13.000s	91.470us	50	50	100.00
		aes_sideload	14.000s	193.203us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	202.339us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	10.555ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	50.486us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	488.682us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	488.682us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	80.043us	5	5	100.00
		aes_csr_rw	7.000s	72.928us	20	20	100.00
		aes_csr_aliasing	5.000s	87.051us	5	5	100.00
		aes_same_csr_outstanding	5.000s	98.675us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	80.043us	5	5	100.00
		aes_csr_rw	7.000s	72.928us	20	20	100.00
		aes_csr_aliasing	5.000s	87.051us	5	5	100.00
		aes_same_csr_outstanding	5.000s	98.675us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	67.203us	50	50	100.00
V2S	fault_inject	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	162.494us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	162.494us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	162.494us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	162.494us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	385.485us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.521ms	5	5	100.00
		aes_tl_intg_err	9.000s	263.020us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	263.020us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	744.868us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	162.494us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	59.614us	50	50	100.00
		aes_stress	13.000s	91.470us	50	50	100.00
		aes_alert_reset	14.000s	744.868us	50	50	100.00
		aes_core_fi	6.467m	10.014ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	162.494us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	88.739us	50	50	100.00
		aes_stress	13.000s	91.470us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	91.470us	50	50	100.00
		aes_sideload	14.000s	193.203us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	88.739us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	88.739us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	88.739us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	88.739us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	88.739us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	91.470us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	91.470us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	13.000s	250.387us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
		aes_ctr_fi	9.000s	55.489us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	13.000s	250.387us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	36.659ms	317	350	90.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	13.000s	250.387us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_ctr_fi	9.000s	55.489us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
		aes_ctr_fi	9.000s	55.489us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	744.868us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
		aes_ctr_fi	9.000s	55.489us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
		aes_ctr_fi	9.000s	55.489us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_ctr_fi	9.000s	55.489us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	13.000s	250.387us	50	50	100.00
		aes_control_fi	47.000s	16.445ms	277	300	92.33
		aes_cipher_fi	48.000s	36.659ms	317	350	90.57
V2S		TOTAL			926	985	94.01
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	9.000m	19.919ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1532	1602	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.46	94.26	98.81	93.39	97.72	92.59	98.85	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_control_fi has 14 failures.
  - 17.aes_control_fi.31675644546227504561349829052316156070241598893691949110536511531995734694244
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:2a5b88ac-15d5-4644-8564-faeb640b8ab2
```
  - 52.aes_control_fi.40148234402243539362782294090811364359017828069704463786147950679562579423863
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:ae9d7273-0b2a-4e95-9324-4c5883a673a4
```
  - ... and 12 more failures.
- Test aes_ctr_fi has 1 failures.
  - 29.aes_ctr_fi.86293405258240056224682217091297449354138924939263683106315706439119982345537
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_ctr_fi/latest/run.log
```
  Job ID: smart:4e9a0bfc-03fb-4c10-9c78-ace64f74f791
```
- Test aes_cipher_fi has 16 failures.
  - 36.aes_cipher_fi.18714900060049050315124898208794185610634958739252290452833882821861454625366
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7883e380-3527-4db1-bf21-a4bd1a5e9c2e
```
  - 46.aes_cipher_fi.12283998598986060247329621097440979748973340132968431546540266078444901856260
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e81c5da2-8b56-4822-ae96-2474da851adb
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 17 failures:
- Test aes_cipher_fi has 17 failures.
  - 19.aes_cipher_fi.70762724284484914345872938991645481296099117667043106730245475921937327350030
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10039222475 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039222475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.aes_cipher_fi.30460774517481289691717791742588997035649134983468909026888584511307905438230
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003162740 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003162740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 31.aes_control_fi.11307664203982156401644780052098000486128209888060513326200155413052504046028
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004213604 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004213604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_control_fi.3248877233773006918018793200680528220225754065202572246701331517416088158766
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003687505 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003687505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.72781103769083191289383760024649178245466031759509530785903149503452983535391
Line 917, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 427343654 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 427343654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.13000294317580425582377580193518162851866337006880801337876895368220898910299
Line 1844, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 555712643 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 555712643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 15.aes_core_fi.80463254911925222563306675914137343871798815991166156209171399000634505539697
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10027333043 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x44d00d84) == 0x0
  UVM_INFO @ 10027333043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.100196384184923282611942030942884337866924688186288760949110078501957202678313
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013789827 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x4557d684) == 0x0
  UVM_INFO @ 10013789827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.62529015148852920651199270946131142787631525932097881683352540031514262627023
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110279170 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 110279170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.100217469931696137529369186213137116031041934356462232828582513073279644346526
    Line 1683, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2469582655 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2469582655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.aes_csr_mem_rw_with_rand_reset.104478263412705206131958690772792850670842612212172788183821611021540217365541
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1289602456 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1289602456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```