AES/UNMASKED Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	69.785us	1	1	100.00
V1	smoke	aes_smoke	4.000s	68.664us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	59.564us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	83.317us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	324.053us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	578.589us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	12.000s	58.273us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	83.317us	20	20	100.00
		aes_csr_aliasing	5.000s	578.589us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	68.664us	50	50	100.00
		aes_config_error	13.000s	509.755us	50	50	100.00
		aes_stress	5.000s	125.772us	50	50	100.00
V2	key_length	aes_smoke	4.000s	68.664us	50	50	100.00
		aes_config_error	13.000s	509.755us	50	50	100.00
		aes_stress	5.000s	125.772us	50	50	100.00
V2	back2back	aes_stress	5.000s	125.772us	50	50	100.00
		aes_b2b	12.000s	151.600us	50	50	100.00
V2	backpressure	aes_stress	5.000s	125.772us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	68.664us	50	50	100.00
		aes_config_error	13.000s	509.755us	50	50	100.00
		aes_stress	5.000s	125.772us	50	50	100.00
		aes_alert_reset	5.000s	104.123us	49	50	98.00
V2	failure_test	aes_man_cfg_err	4.000s	63.258us	50	50	100.00
		aes_config_error	13.000s	509.755us	50	50	100.00
		aes_alert_reset	5.000s	104.123us	49	50	98.00
V2	trigger_clear_test	aes_clear	7.000s	221.274us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	112.618us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	104.123us	49	50	98.00
V2	stress	aes_stress	5.000s	125.772us	50	50	100.00
V2	sideload	aes_stress	5.000s	125.772us	50	50	100.00
		aes_sideload	5.000s	103.273us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	227.301us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	1.643ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	67.898us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	118.099us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	118.099us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	59.564us	5	5	100.00
		aes_csr_rw	8.000s	83.317us	20	20	100.00
		aes_csr_aliasing	5.000s	578.589us	5	5	100.00
		aes_same_csr_outstanding	8.000s	141.064us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	59.564us	5	5	100.00
		aes_csr_rw	8.000s	83.317us	20	20	100.00
		aes_csr_aliasing	5.000s	578.589us	5	5	100.00
		aes_same_csr_outstanding	8.000s	141.064us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	5.000s	105.073us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	12.000s	71.309us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	12.000s	71.309us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	12.000s	71.309us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	12.000s	71.309us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	18.000s	161.965us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	261.071us	5	5	100.00
		aes_tl_intg_err	9.000s	409.302us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	409.302us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	104.123us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	12.000s	71.309us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	68.664us	50	50	100.00
		aes_stress	5.000s	125.772us	50	50	100.00
		aes_alert_reset	5.000s	104.123us	49	50	98.00
		aes_core_fi	3.500m	10.020ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	12.000s	71.309us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	77.979us	50	50	100.00
		aes_stress	5.000s	125.772us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	125.772us	50	50	100.00
		aes_sideload	5.000s	103.273us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	77.979us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	77.979us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	77.979us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	77.979us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	77.979us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	125.772us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	125.772us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	123.990us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
		aes_ctr_fi	4.000s	63.482us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	123.990us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	78.749ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	123.990us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_ctr_fi	4.000s	63.482us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
		aes_ctr_fi	4.000s	63.482us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	104.123us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
		aes_ctr_fi	4.000s	63.482us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
		aes_ctr_fi	4.000s	63.482us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_ctr_fi	4.000s	63.482us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	123.990us	48	50	96.00
		aes_control_fi	46.000s	32.842ms	276	300	92.00
		aes_cipher_fi	49.000s	78.749ms	323	350	92.29
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.067m	12.084ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1533	1602	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.52	94.39	98.81	93.63	97.72	93.33	98.66	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 18 failures.
  - 4.aes_control_fi.106940441774556177349622775552461945413331881308404930835921316707075750022067
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:1000a592-1eeb-4075-84b4-f1945cc097d5
```
  - 35.aes_control_fi.5236405025427784495886733645074547687547385015435025781793618794649195578720
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:842fdfd3-5e16-44fc-be4f-8fd543881d1b
```
  - ... and 16 more failures.
- Test aes_cipher_fi has 12 failures.
  - 76.aes_cipher_fi.115783280167638652218496405830451305621989084071478618260014444157379134521471
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1f38bdf6-9879-464a-9e72-9ec1d66f0274
```
  - 77.aes_cipher_fi.3971156163491861079770769969219457390069012905750803501332007242650239755140
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/77.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b9ddb89c-fb94-4570-b07e-300ee9f03596
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 44.aes_cipher_fi.65030190151628824940136635202199039511307764648252402425144579138000588473198
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007689013 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007689013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 71.aes_cipher_fi.97076784594844058834471720689611291440148383210993044939395277387442290438016
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/71.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007776839 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007776839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.111826770522865067349015275078044612357488103209092202767376115526705422818797
Line 997, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 893877194 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 893877194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.9608136547472530030783364943766418559288813939890596391341161317578699538709
Line 603, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1050033641 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1050033641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 41.aes_control_fi.43393971281908582776089782405238402092670369776853211172195400673828461459370
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007922075 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007922075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_control_fi.64819482217371232364120899191939030564577582566410881078872566699985046732869
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003160346 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003160346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.74932510090303195425605736882694892555427282451396771798464041765423804175380
Line 463, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12084094773 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 12084094773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.72687649876886112748854808762709469668898168226648397097468066791930294319581
Line 715, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 577060033 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 577060033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 16.aes_core_fi.115653544944674321807444574164817429377341259618839571601389787366051460222900
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015009534 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015009534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_core_fi.103715076092538068490017063842798426217742711999612096726860417087560433869181
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006723621 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006723621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 1 failures.

21.aes_fi.102233915956094369472970659702907479254293640580533764889306897977550142067866
Line 1755, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 93377582 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 93177582 PS)
  UVM_ERROR @  93377582 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  93377582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_alert_reset has 1 failures.

25.aes_alert_reset.94830719429527753589565271148795963178099370329813269425802215211043036820655
Line 2596, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 58049650 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 58029242 PS)
  UVM_ERROR @  58049650 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  58049650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 15.aes_fi.59750210462519212307948236226540111454342452925830869706860355772533686963898
    Line 1434, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 4599554 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 4589137 PS)
  UVM_ERROR @   4599554 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   4599554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 47.aes_core_fi.3412496945460908269725529863630171268182719956853888369508023459874366823943
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020378785 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x2f29ad84) == 0x0
  UVM_INFO @ 10020378785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 66.aes_cipher_fi.21455452254980381945250966597265567713188083342894993560511594516662089295634
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  40362335 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  40362335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```