AES/UNMASKED Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: `d51405297e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	90.740us	1	1	100.00
V1	smoke	aes_smoke	7.000s	195.978us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	95.837us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	88.563us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.894ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	87.317us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	69.428us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	88.563us	20	20	100.00
		aes_csr_aliasing	4.000s	87.317us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	195.978us	50	50	100.00
		aes_config_error	12.000s	326.546us	50	50	100.00
		aes_stress	9.000s	79.680us	50	50	100.00
V2	key_length	aes_smoke	7.000s	195.978us	50	50	100.00
		aes_config_error	12.000s	326.546us	50	50	100.00
		aes_stress	9.000s	79.680us	50	50	100.00
V2	back2back	aes_stress	9.000s	79.680us	50	50	100.00
		aes_b2b	16.000s	308.213us	50	50	100.00
V2	backpressure	aes_stress	9.000s	79.680us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	195.978us	50	50	100.00
		aes_config_error	12.000s	326.546us	50	50	100.00
		aes_stress	9.000s	79.680us	50	50	100.00
		aes_alert_reset	8.000s	77.395us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	54.995us	50	50	100.00
		aes_config_error	12.000s	326.546us	50	50	100.00
		aes_alert_reset	8.000s	77.395us	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	95.556us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	619.196us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	77.395us	50	50	100.00
V2	stress	aes_stress	9.000s	79.680us	50	50	100.00
V2	sideload	aes_stress	9.000s	79.680us	50	50	100.00
		aes_sideload	14.000s	151.375us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	64.504us	50	50	100.00
V2	stress_all	aes_stress_all	43.000s	1.671ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	54.858us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	92.683us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	92.683us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	95.837us	5	5	100.00
		aes_csr_rw	3.000s	88.563us	20	20	100.00
		aes_csr_aliasing	4.000s	87.317us	5	5	100.00
		aes_same_csr_outstanding	4.000s	183.827us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	95.837us	5	5	100.00
		aes_csr_rw	3.000s	88.563us	20	20	100.00
		aes_csr_aliasing	4.000s	87.317us	5	5	100.00
		aes_same_csr_outstanding	4.000s	183.827us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	141.072us	49	50	98.00
V2S	fault_inject	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	275.023us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	275.023us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	275.023us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	275.023us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	95.625us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	338.137us	5	5	100.00
		aes_tl_intg_err	5.000s	440.417us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	440.417us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	77.395us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	275.023us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	195.978us	50	50	100.00
		aes_stress	9.000s	79.680us	50	50	100.00
		aes_alert_reset	8.000s	77.395us	50	50	100.00
		aes_core_fi	6.583m	10.012ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	275.023us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	86.954us	50	50	100.00
		aes_stress	9.000s	79.680us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	79.680us	50	50	100.00
		aes_sideload	14.000s	151.375us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	86.954us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	86.954us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	86.954us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	86.954us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	86.954us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	79.680us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	79.680us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	73.984us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
		aes_ctr_fi	8.000s	70.702us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	73.984us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	42.592ms	318	350	90.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	73.984us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_ctr_fi	8.000s	70.702us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
		aes_ctr_fi	8.000s	70.702us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	77.395us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
		aes_ctr_fi	8.000s	70.702us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
		aes_ctr_fi	8.000s	70.702us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_ctr_fi	8.000s	70.702us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	73.984us	48	50	96.00
		aes_control_fi	48.000s	65.639ms	272	300	90.67
		aes_cipher_fi	50.000s	42.592ms	318	350	90.86
V2S		TOTAL			919	985	93.30
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.633m	128.291ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1526	1602	95.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.11	97.41	94.14	98.75	93.65	97.72	91.11	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 40 failures:
- Test aes_control_fi has 15 failures.
  - 0.aes_control_fi.59800412077461088109458223577272214790751580992427981492603676687053239317046
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:a0fca5da-da33-430a-a3a4-7e39a1efa0ec
```
  - 21.aes_control_fi.102435368229654694456975959681317832418556949284545274720905905781599590692129
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job ID: smart:51e846b8-f7d7-4053-94e5-6858b0b44be8
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 25 failures.
  - 16.aes_cipher_fi.35817408601619865554892271087751399530418625593374595193403348016826270319607
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job ID: smart:93c47160-39d8-4c51-a356-866503c6b5df
```
  - 36.aes_cipher_fi.23594531325087217752092144152844535060402511780936560496773118099798465422045
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c25cd318-1e53-4244-bb70-bf121130d90f
```
  - ... and 23 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 7.aes_control_fi.99340303126953799737145171797150336396331961852392364656410396165543615858114
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013017658 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013017658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.aes_control_fi.87914400668720848283379097477800394544810295535214616976473948136059104801083
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005145873 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005145873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 14.aes_cipher_fi.80681992658512581368840776136620082442479152428977366105890643870270175451509
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007525622 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007525622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 86.aes_cipher_fi.109993079726259310519702680778632546960073422989382180547137699062579811790952
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/86.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016713020 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016713020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.99495857809925348389930264305398423381430252817883175970530137507444465748891
Line 1196, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 303521876 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 303521876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.71786354772481493171497388770772782778459453634985191128125345780296839407757
Line 1104, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 128290808027 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 128290808027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.55943577427542473167152367297831447250489014878488289141501961681468972839335
Line 1331, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 345295946 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 345295946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.93205498930971168829212888025845876204656681347100129773066604045938589721065
Line 732, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 331489391 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 331489391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 3 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

6.aes_stress_all_with_rand_reset.22363778443561151123395791869008799839675649330116806885117805952872283637279
Line 1432, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 581039470 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 581029470 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 581039470 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 581029470 PS)
  UVM_ERROR @ 581039470 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

Test aes_fi has 2 failures.

15.aes_fi.18521338553822499870678388726419321971815154248273420064767531677912579842471
Line 2685, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 21051569 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 21024542 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 21051569 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 21024542 PS)
  UVM_ERROR @  21051569 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

49.aes_fi.38069554251415233482835986564910957418879880192363152757212617727292781859535
Line 4437, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 18153106 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 18143106 PS)
  UVM_ERROR @  18153106 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  18153106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 6.aes_core_fi.23452115010926320565065340157608675622408472438834995967265423761055906595846
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10034793570 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xe0d92284) == 0x0
  UVM_INFO @ 10034793570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.aes_core_fi.6248489451581113464766047163073380520127515812865232408070179252128967678406
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011781856 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf4885684) == 0x0
  UVM_INFO @ 10011781856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 28.aes_reseed.94432973606218361373911231430086306606642819536066617391026323941446585181153
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_reseed/latest/run.log
```
  UVM_FATAL @  63599832 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  63599832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 38.aes_core_fi.13200144232336958898120429390561572328017324143449614822112779614970509150890
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004609683 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004609683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```