AES/UNMASKED Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	91.330us	1	1	100.00
V1	smoke	aes_smoke	12.000s	175.398us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	125.858us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	54.927us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.565ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	359.567us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	93.544us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	54.927us	20	20	100.00
		aes_csr_aliasing	4.000s	359.567us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	12.000s	175.398us	50	50	100.00
		aes_config_error	9.000s	195.448us	50	50	100.00
		aes_stress	13.000s	124.165us	50	50	100.00
V2	key_length	aes_smoke	12.000s	175.398us	50	50	100.00
		aes_config_error	9.000s	195.448us	50	50	100.00
		aes_stress	13.000s	124.165us	50	50	100.00
V2	back2back	aes_stress	13.000s	124.165us	50	50	100.00
		aes_b2b	18.000s	113.158us	50	50	100.00
V2	backpressure	aes_stress	13.000s	124.165us	50	50	100.00
V2	multi_message	aes_smoke	12.000s	175.398us	50	50	100.00
		aes_config_error	9.000s	195.448us	50	50	100.00
		aes_stress	13.000s	124.165us	50	50	100.00
		aes_alert_reset	8.000s	135.218us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	72.744us	50	50	100.00
		aes_config_error	9.000s	195.448us	50	50	100.00
		aes_alert_reset	8.000s	135.218us	50	50	100.00
V2	trigger_clear_test	aes_clear	19.000s	128.823us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	733.074us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	135.218us	50	50	100.00
V2	stress	aes_stress	13.000s	124.165us	50	50	100.00
V2	sideload	aes_stress	13.000s	124.165us	50	50	100.00
		aes_sideload	10.000s	186.112us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	106.517us	50	50	100.00
V2	stress_all	aes_stress_all	43.000s	2.024ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	63.111us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	461.460us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	461.460us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	125.858us	5	5	100.00
		aes_csr_rw	4.000s	54.927us	20	20	100.00
		aes_csr_aliasing	4.000s	359.567us	5	5	100.00
		aes_same_csr_outstanding	4.000s	982.682us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	125.858us	5	5	100.00
		aes_csr_rw	4.000s	54.927us	20	20	100.00
		aes_csr_aliasing	4.000s	359.567us	5	5	100.00
		aes_same_csr_outstanding	4.000s	982.682us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	106.304us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	84.048us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	84.048us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	84.048us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	84.048us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	167.467us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	530.562us	5	5	100.00
		aes_tl_intg_err	5.000s	202.720us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	202.720us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	135.218us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	84.048us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	12.000s	175.398us	50	50	100.00
		aes_stress	13.000s	124.165us	50	50	100.00
		aes_alert_reset	8.000s	135.218us	50	50	100.00
		aes_core_fi	23.000s	10.008ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	84.048us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	69.954us	50	50	100.00
		aes_stress	13.000s	124.165us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	124.165us	50	50	100.00
		aes_sideload	10.000s	186.112us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	69.954us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	69.954us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	69.954us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	69.954us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	69.954us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	124.165us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	124.165us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	399.999us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
		aes_ctr_fi	8.000s	60.845us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	399.999us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	16.442ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	399.999us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_ctr_fi	8.000s	60.845us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
		aes_ctr_fi	8.000s	60.845us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	135.218us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
		aes_ctr_fi	8.000s	60.845us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
		aes_ctr_fi	8.000s	60.845us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_ctr_fi	8.000s	60.845us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	399.999us	50	50	100.00
		aes_control_fi	46.000s	30.920ms	278	300	92.67
		aes_cipher_fi	48.000s	16.442ms	326	350	93.14
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.533m	16.884ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1542	1602	96.25

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.06	97.35	94.01	98.71	93.60	97.72	91.11	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
- Test aes_cipher_fi has 13 failures.
  - 4.aes_cipher_fi.19442864274267452648538714516034232902853972466360879424988410190266715999971
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:6a13c046-8373-4326-835c-5248933ce47c
```
  - 42.aes_cipher_fi.52206899290373835609392386570196810665341609636425968509155304614852152341526
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  Job ID: smart:700095a3-c7df-4d60-ac8d-2d29e58b3a33
```
  - ... and 11 more failures.
- Test aes_control_fi has 12 failures.
  - 14.aes_control_fi.78806055227826924046476062430018656321555588538826036265334278556672430990501
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job ID: smart:75d30948-cb97-465e-86f4-67ffd31bb434
```
  - 59.aes_control_fi.30277020509916993871217624773503794698942016739531741545304148844482289189643
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  Job ID: smart:cad1eae0-38d8-4306-979f-e4888fd2118c
```
  - ... and 10 more failures.
- Test aes_ctr_fi has 1 failures.
  - 41.aes_ctr_fi.40865992002281684389311587952960328548369897868168430685382047774749339001705
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_ctr_fi/latest/run.log
```
  Job ID: smart:233f7eef-05cc-4ce1-9ded-79730bb478f8
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 4.aes_control_fi.36799551868452628638072553540072396715639276804995137350169654508983056298658
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005484185 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005484185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_control_fi.20620699946533131768783649200352153818776371355434133035370642501808187868721
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009232648 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009232648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 56.aes_cipher_fi.60206630312363444927797004422130620876019141532844190668268628067288301834282
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003032642 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003032642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 170.aes_cipher_fi.39953531781999092617217815127376118318181611561031996620044760161719517411596
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/170.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006902709 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006902709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

1.aes_stress_all_with_rand_reset.39282934870752733773133947226703735883399448359688424935642202715840193657265
Line 557, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3178392003 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3178392003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.62165122599369591996212291254938402390472995664579560208815397655779194412608
Line 649, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 274479285 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 274479285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 3.aes_core_fi.1741332440643137808009985874574472666485023500598858292911723268971828331829
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010543685 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010543685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.aes_core_fi.59946131573833431260362285049804788100648132163252778952112035186698266344491
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10061103985 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10061103985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.36845968730884922880679665093638890491593452980537503430504747810236437813486
    Line 1932, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 657860088 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 657860088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 113.aes_cipher_fi.25696950709988449980163226223925571698830204049832225984173648473287112973566
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```