AES/UNMASKED Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	62.640us	1	1	100.00
V1	smoke	aes_smoke	14.000s	50.834us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	171.605us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	76.977us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	183.051us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	967.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	386.951us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	76.977us	20	20	100.00
		aes_csr_aliasing	5.000s	967.313us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	50.834us	50	50	100.00
		aes_config_error	16.000s	178.352us	50	50	100.00
		aes_stress	9.000s	149.146us	50	50	100.00
V2	key_length	aes_smoke	14.000s	50.834us	50	50	100.00
		aes_config_error	16.000s	178.352us	50	50	100.00
		aes_stress	9.000s	149.146us	50	50	100.00
V2	back2back	aes_stress	9.000s	149.146us	50	50	100.00
		aes_b2b	9.000s	1.104ms	50	50	100.00
V2	backpressure	aes_stress	9.000s	149.146us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	50.834us	50	50	100.00
		aes_config_error	16.000s	178.352us	50	50	100.00
		aes_stress	9.000s	149.146us	50	50	100.00
		aes_alert_reset	8.000s	76.182us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	62.827us	50	50	100.00
		aes_config_error	16.000s	178.352us	50	50	100.00
		aes_alert_reset	8.000s	76.182us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	260.891us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	413.539us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	76.182us	50	50	100.00
V2	stress	aes_stress	9.000s	149.146us	50	50	100.00
V2	sideload	aes_stress	9.000s	149.146us	50	50	100.00
		aes_sideload	9.000s	286.987us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	160.982us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	1.230ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	102.145us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	177.461us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	177.461us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	171.605us	5	5	100.00
		aes_csr_rw	4.000s	76.977us	20	20	100.00
		aes_csr_aliasing	5.000s	967.313us	5	5	100.00
		aes_same_csr_outstanding	5.000s	595.789us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	171.605us	5	5	100.00
		aes_csr_rw	4.000s	76.977us	20	20	100.00
		aes_csr_aliasing	5.000s	967.313us	5	5	100.00
		aes_same_csr_outstanding	5.000s	595.789us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	271.714us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	82.424us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	82.424us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	82.424us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	82.424us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	1.055ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.356ms	5	5	100.00
		aes_tl_intg_err	5.000s	472.593us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	472.593us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	76.182us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	82.424us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	50.834us	50	50	100.00
		aes_stress	9.000s	149.146us	50	50	100.00
		aes_alert_reset	8.000s	76.182us	50	50	100.00
		aes_core_fi	1.817m	10.036ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	82.424us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	70.463us	50	50	100.00
		aes_stress	9.000s	149.146us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	149.146us	50	50	100.00
		aes_sideload	9.000s	286.987us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	70.463us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	70.463us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	70.463us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	70.463us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	70.463us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	149.146us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	149.146us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	117.219us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
		aes_ctr_fi	7.000s	174.461us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	117.219us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	31.530ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	117.219us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_ctr_fi	7.000s	174.461us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
		aes_ctr_fi	7.000s	174.461us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	76.182us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
		aes_ctr_fi	7.000s	174.461us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
		aes_ctr_fi	7.000s	174.461us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_ctr_fi	7.000s	174.461us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	117.219us	50	50	100.00
		aes_control_fi	44.000s	10.003ms	275	300	91.67
		aes_cipher_fi	48.000s	31.530ms	322	350	92.00
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	1.453ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1535	1602	95.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.48	94.31	98.81	93.74	97.72	93.33	98.85	96.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_cipher_fi has 19 failures.
  - 3.aes_cipher_fi.98038434457352692861839595224243123619888816070071213847144791833653670396170
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cd00e0d6-72b6-4816-b2b8-1573e661d496
```
  - 8.aes_cipher_fi.38536768552053021596571251612469799704852794595010838899145539592453567205301
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  Job ID: smart:000ab823-8c60-473b-913b-0fce3afe8d9e
```
  - ... and 17 more failures.
- Test aes_control_fi has 13 failures.
  - 17.aes_control_fi.29513876106026560293449295333430405751826665874473771954244474230443830361147
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:b0c86901-1667-489b-9c24-cb79ead93932
```
  - 52.aes_control_fi.58090285728697691276940316515484725245534402531685808782032415237363143288992
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  Job ID: smart:885b1af2-198e-4a9a-9564-0ad13f9d81e3
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 0.aes_control_fi.48580347080250807355035391057048223107176314440051911972610575238515419019263
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010435487 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010435487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.aes_control_fi.18798251620571356469765894514501376642540519504378806711718052064779709261290
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006901504 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006901504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 19.aes_cipher_fi.86751368556256709760254674454139810158898721265072921448112430454689056768372
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008698760 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008698760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_cipher_fi.60300900884747394251001117116621612168119130070084234246468421358635972207436
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003099237 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003099237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.23768978698186669429208950422671756049718802306436484447917044978800619858144
Line 1243, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1224386898 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1224386898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.113236924154999272661254734452979994687539847627204478656797484822463608258106
Line 1104, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1453362208 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1453362208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 29.aes_core_fi.20418336167100877682948962304510625264711716755453339411198002600889451932363
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004477492 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004477492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_core_fi.97837344306406253156889058558628201076035572004706697304197392289763720368770
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007706061 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007706061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.52929918741720770359372742227329961417551402642310510946481051531958362462513
    Line 765, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 1264332894 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 1264291227 PS)
  UVM_ERROR @ 1264332894 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 1264332894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.14448341900146728806503773367036824154244945655202392106679868946757406894827
    Line 631, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 674336524 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 674336524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.11117305695962036181424132526767328152195116310549980552447636827338529869272
    Line 581, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 199855288 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 199834455 PS)
  UVM_ERROR @ 199855288 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 199855288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 65.aes_core_fi.90357923970483700391268648310643577489362304046496298332397053983480201728380
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035950410 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x854d784) == 0x0
  UVM_INFO @ 10035950410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 321.aes_cipher_fi.43163050694424108962692114670872130966075337678326362443224674488342622933287
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/321.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @  24638597 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  24638597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```