AON_TIMER Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.460s 576.258us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.420s 1.220ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.320s 463.583us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 11.320s 5.476ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.580s 613.753us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.550s 574.680us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.320s 463.583us 20 20 100.00
aon_timer_csr_aliasing 1.580s 613.753us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 0.800s 488.393us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.290s 504.080us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.396m 53.202ms 50 50 100.00
V2 jump aon_timer_jump 1.520s 562.880us 50 50 100.00
V2 stress_all aon_timer_stress_all 5.558m 200.139ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.310s 501.923us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.970s 606.466us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.970s 606.466us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.420s 1.220ms 5 5 100.00
aon_timer_csr_rw 1.320s 463.583us 20 20 100.00
aon_timer_csr_aliasing 1.580s 613.753us 5 5 100.00
aon_timer_same_csr_outstanding 6.200s 1.755ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.420s 1.220ms 5 5 100.00
aon_timer_csr_rw 1.320s 463.583us 20 20 100.00
aon_timer_csr_aliasing 1.580s 613.753us 5 5 100.00
aon_timer_same_csr_outstanding 6.200s 1.755ms 20 20 100.00
V2 TOTAL 240 240 100.00
V2S tl_intg_err aon_timer_sec_cm 6.980s 3.944ms 5 5 100.00
aon_timer_tl_intg_err 13.330s 8.747ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.330s 8.747ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 14.298m 455.061ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 430 430 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.46 99.82 94.68 100.00 -- 99.35 100.00 96.90

Past Results