AON_TIMER Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	601.895us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.890s	1.055ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	510.835us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	39.700s	13.846ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.410s	553.604us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.590s	491.390us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	510.835us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	553.604us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.320s	502.432us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.120s	424.848us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.298m	52.640ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	603.855us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.640m	276.329ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.310s	504.818us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.870s	569.274us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.870s	569.274us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.890s	1.055ms	5	5	100.00
		aon_timer_csr_rw	1.380s	510.835us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	553.604us	5	5	100.00
		aon_timer_same_csr_outstanding	6.720s	2.349ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.890s	1.055ms	5	5	100.00
		aon_timer_csr_rw	1.380s	510.835us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	553.604us	5	5	100.00
		aon_timer_same_csr_outstanding	6.720s	2.349ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	13.280s	7.542ms	5	5	100.00
		aon_timer_tl_intg_err	15.530s	8.522ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.530s	8.522ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.170m	155.198ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 6 failures:

Test aon_timer_stress_all_with_rand_reset has 5 failures.

1.aon_timer_stress_all_with_rand_reset.113737553017626664146714484588084382046905800297597494859658224368463359929283
Line 378, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7847332933 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7847332933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aon_timer_stress_all_with_rand_reset.88429545895043313401820362338991578667354258812445067602538455165109944657348
Line 678, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 61629164665 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 61629164665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all has 1 failures.

42.aon_timer_stress_all.51191297882849146167825526705551040341767607779896659806185786108928052672049
Line 261, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 34901040305 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 34901040305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:282) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 35.aon_timer_stress_all.78685543976759016761695066581957349428202051243917114803831060997026095848787
    Line 309, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/35.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 157724608612 ps: (aon_timer_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 157724608612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```