AON_TIMER Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.560s	456.220us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.690s	744.345us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	501.592us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	37.620s	9.972ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.320s	676.337us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	539.275us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	501.592us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	676.337us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.240s	498.703us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.340s	502.504us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.567m	55.758ms	50	50	100.00
V2	jump	aon_timer_jump	1.550s	579.144us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.201m	269.555ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.410s	481.302us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.800s	376.796us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.800s	376.796us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.690s	744.345us	5	5	100.00
		aon_timer_csr_rw	1.380s	501.592us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	676.337us	5	5	100.00
		aon_timer_same_csr_outstanding	8.220s	3.009ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.690s	744.345us	5	5	100.00
		aon_timer_csr_rw	1.380s	501.592us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	676.337us	5	5	100.00
		aon_timer_same_csr_outstanding	8.220s	3.009ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	11.880s	7.535ms	5	5	100.00
		aon_timer_tl_intg_err	14.510s	8.863ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.510s	8.863ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.362m	217.926ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.02	99.25	93.67	100.00	--	98.40	99.51	67.30

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

10.aon_timer_stress_all_with_rand_reset.11062284440069476351053168503095372726416429262150185520321520754855724127203
Line 854, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 104957491325 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 104957491325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.aon_timer_stress_all_with_rand_reset.43400039458249279905793472500097498601332606183662754246034785085343493308069
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 583365443 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 583365443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 5 failures.

26.aon_timer_stress_all.56025634728370563998347514372796191052264702709888049683389385551398217848018
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1602867234 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1602867234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.aon_timer_stress_all.43737583200750558831255822908132761856894600083289831960756563579590020117737
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 507333085 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 507333085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.